andrew@frip.gwd.tek.com (Andrew Klossner) (01/21/89)
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"Incidentally, the next Motorola processor (the RISC 88000)
requires a non-linear code, since its speed can be degradated
if one instruction needs the result coming from one of the
previous two or three steps. 88000 compilers are designed to
"jump" from one logical phase to another as much as possible,
to use the intrinsic parallelism of this machine."
This isn't strictly true. Most 88k instructions complete in one cycle
and their results are immediately available to the next instruction.
(In fact, there is forwarding logic in place to avoid the delay
involved in writing a result to a register then reading it out right
away.)
The only instructions whose results can be delayed are load (from
memory), integer multiply/divide, and floating point. A good compiler
will attempt to organize the object code so that results from these
instructions are not needed before they are available.
-=- Andrew Klossner (uunet!tektronix!hammer!frip!andrew) [UUCP]
(andrew%frip.gwd.tek.com@relay.cs.net) [ARPA]