rbt@cernvax.UUCP (rbt) (04/07/89)
Bad news for all the MC68030 users. The Cache Inhibit Input CIIN line may not work 100% of the times. This is our environment: a MC68030 is mounted of a FASTBUS board. The processor addressing space is divided into 8 banks, each one has a specific function. Many of these banks are used for communication purposes and the processor must not cache those values, since they are changed asynchronously by external devices (DUART, I/O ports etc...). So, the CIIN line has been used to prevent data from being loaded into the MC68030 data cache (see MC68030 USER'S MANUAL, 5.7.1 and 6.1). This line is asserted low every time the processor accesses one of the banks corresponding to an external device. And here is our problem: the location $60000100 IS CACHED, even if the CIIN line is asserted low. This is not always true: infact it happens only when the Cache Control Register CACR Write Allocate WA (see 6.1.2.1 and 6.3.1.1) bit is set! I have been able to reproduce the problem running a simple test program that never changes it mode. So, the WA bit should not change the symptom. Unfortunately it does. When the write-allocate mode is enabled the data coming from this key address is cached. Now, we had a look at the releases notes for MC68030 and there are lots of bug reports concerning processor references at memory locations placed on page boundary, but it seems to me that they are all related to the on-chip Memory Management Unit (MMU). We are running with the MMU disabled. So, for the time being we will disable the write-allocate mode. -- +-----------------------+----------------------------------------------+ | Roberto Divia` | Love at first sight is one of the greatest | | ============= | labor-saving devices the world has ever seen | +-----------------------+----------------------------------------------+