ben@grace.UUCP (Ben Henwood) (06/30/89)
I hope this is an appropriate news group for a VMEbus question. Anyway, my group is experiencing some problems in a system with a Sun 3/280s, a Mercury ZIP array processor, and a Bit 3 VMEbus to VMEbus interface card (amoung other things). For some reason the Sun gets a slug of spurrious interrupts after an interrupt acknowledge by register read on the Mercury ZIP, and we aren't sure why yet. But one question has come to mind about the VMEbus RULE 4.5 in our search for an answer: why is there a 2 microsecond specification for releasing the interrupt request line? Is it a requirement to enable the interrupt handler to discern two simultaneous interrupts at the same level (while providing a realistic design time limit)? If there is some other reason, I'd like to know. We could use all the help we can get. We have been unsuccessful in triggering our logic analyzer on any set of signals that would reveal exactly what happens at the instant the VMEbus fouls up; we just know that hundreds of spurrious interrupts occur suddently and unpredictably. Thanks for any help! Ben Henwood Applied Physics Lab/UW ben@apl-uw.apl.washington.edu ben@grace.apl.washington.edu