dvadura@watdragon.waterloo.edu (Dennis Vadura) (06/30/89)
We are in the process of implementing an OS on a system with four 68030 cpu's. We are having trouble with the 030 data cache during context switches. We seem unable to flush the data cache on context switch and obtain consistent behaviour. It appears as if some values remain cached after the context switch. In addition, the behaviour seems to be dependent on the sequence of instructions prior to and after the cache reset code. In some instances it works and in others it does not, and it appears to be somewhat random, ie. we have not discovered the reason why a particular sequence works or does not. The cache is cleared after changing the page table root pointer using code that looks like: movl 0x909, %d0 movl %d0, %cacr Does anyone have any experience with using the data cache? Code, comments, speculation are all welcome. If you need more info send mail. NOTE: We have no problem with the instruction cache. -dennis -- -------------------------------------------------------------------------------- Death is an experience that is best |Dennis UUCP,BITNET: dvadura@water shared. [Lt. Worf] |Vadura EDU,CDN,CSNET: dvadura@waterloo ================================================================================
bruce@heather.pooh.com (Bruce Robertson) (07/01/89)
Two things. First, if your sample code really looks like that, the problem is that you're fetching a value from location 0x909 and stashing it in %cacr. You really want to do this: movl &0x909, %d0 movl %d0, %cacr Second, here is a slightly better way to do it: mov.l %cacr,%d0 or.w &0x909,%d0 mov.l %d0,%cacr The above code is straight out of the UNIX kernel I did for the 68030. -- Bruce Robertson Hundred Acre Software, Reno, NV Domain: bruce@pooh.com UUCP: ...!uunet!tahoe.unr.edu!heather!bruce