aleneis@jarthur.Claremont.EDU (Tony Leneis) (11/10/89)
Can anyone clue me in to the differences between the MC68040 and the MC68030? Is there an on-chip math coprocessor on the 040? What about cache types and sizes, deeper or more parallel pipelining, new addressing modes, new instructions, new registers, etc.? Finally, what clock speeds will this beast be available in? Thanks, Tony ------------------------------------------------------------------------------- INTERNET: aleneis@jarthur.claremont.edu BITNET: aleneis@hmcvax.bitnet UUCP: ...uunet!jarthur!aleneis
mslater@cup.portal.com (Michael Z Slater) (11/12/89)
>Can anyone clue me in to the differences between the MC68040 and the >MC68030? Is there an on-chip math coprocessor on the 040? What about cache >types and sizes, deeper or more parallel pipelining, new addressing modes, >new instructions, new registers, etc.? Finally, what clock speeds will this >beast be available in? Moto has not yet formally introduced the 040, and has not given any performance data, other than to say it is more than 2x the 030 (and faster than the 486). It has two 4K caches, an on-chip FPU, and more pipelining. Many simple instructions execute in 1 clock. Clock speeds have not been disclosed. There is only one new instruction, a memory-to-memory block move, that is a supervisor mode instruction. No new user-mode instructions, no new addressing modes. Michael Slater, Microprocessor Report mslater@cup.portal.com 550 California Ave., Suite 320, Palo Alto, CA 94306 415/494-2677
kaufman@Neon.Stanford.EDU (Marc T. Kaufman) (11/13/89)
In article <23948@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes:
-Moto has not yet formally introduced the 040, and has not given any performance
-data, other than to say it is more than 2x the 030 (and faster than the 486).
-It has two 4K caches, an on-chip FPU, and more pipelining...
Its going to be interesting to see if I can buy enough ram to hold the
trap exception frame. :-)
Marc Kaufman (kaufman@Neon.stanford.edu)tomj@oakhill.UUCP (Tom Johnson) (11/14/89)
In article <23948@cup.portal.com> mslater@cup.portal.com writes: >>Can anyone clue me in to the differences between the MC68040 and the >>MC68030? > >Moto has not yet formally introduced the 040, and has not given any performance >data, other than to say it is more than 2x the 030 (and faster than the 486). > >There is only one new instruction, a memory-to-memory block move, that >is a supervisor mode instruction. ^^^^^^^^^^ > >Michael Slater, Microprocessor Report mslater@cup.portal.com >550 California Ave., Suite 320, Palo Alto, CA 94306 415/494-2677 Sorry Michael, but the information you have must be a little outdated...the MOVE16 instruction is NOT a supervisor-only instruction, but rather, is available regardless of the state of the S bit in the status register. We (Motorola) will be releasing more info on the 68040 soon. Tom Johnson Disclaimer: These statements are my own, and don't necessarily reflect the position of my employer.
srg@quick.COM (Spencer Garrett) (11/14/89)
In article <1989Nov12.172830.10798@Neon.Stanford.EDU>, kaufman@Neon.Stanford.EDU (Marc T. Kaufman) writes: -> In article <23948@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes: -> -> -Moto has not yet formally introduced the 040, and has not given any performance -> -data, other than to say it is more than 2x the 030 (and faster than the 486). -> -> -It has two 4K caches, an on-chip FPU, and more pipelining... -> -> Its going to be interesting to see if I can buy enough ram to hold the -> trap exception frame. :-) Actually, since the 040 uses instruction restart instead of instruction continuation, the bus error frame is *smaller* than that of the 030. (And a *lot* smaller than the 030/882 combination.) The code to deal with exceptions will probably be a bit trickier, though.