jon@hpsad.HP.COM (Jon Aldrich) (03/16/90)
Netters, I looking for a source of information on designing a memory expansion board for my computer. What I have in mind might have a title like "Ram Design for the Complete Dweeb" or something like that. (I'm just an ex-tech turned software guy.) :-) I've looked in several different manufacturer's data books and they usually contain a more generalized block diagram. I would like to find a little more specific information. I have an on hand supply of discrete parts, but limited access to any of the new dram controllers; however, I would like to go with the best technology that I can, on the budget I have (low $$$). Ideally I would like to interface some of the 1Mx8 dram modules to my system, although I could live with design examples for any of the 256k/1M/4M drams. I am running a 68010 (12MHz) unix workstation, with plenty of expansion slots. My existing RAM boards are using older 16K chips with an on board refresh driver, (Nat 8402?), driven at 10MHz. Memeory access is intiated async by AS and ended by DTACK after 180us (delay line driven). I'm living on borrowed RAM now and soon that will end. ANY AND ALL SUGGESTIONS WILL BE APPRECIATED !!!!! ------------------------------------------------------------------------- Jon Aldrich Hewlett-Packard "People aren't buying jon@hpsadpk Signal Analysis Division enough hats." telnet (707) 794-3826 1212 Valley House Dr. (1UM) M. Python Rohnert Park CA, 94928 ------------------------------------------------------------------------- Blame the author, not the employer!!
aikc@castle.ed.ac.uk (Kenneth Cameron) (03/18/90)
I spent several weeks trying to track down this type of information.
As you say, most tend to just be block diagrams showing none of the
details. I finally got hold of a book, which not only gave an example
circuit for dynamic refresh control (using 74xx chips), but explained all
the timing that must be considered. It's called
Microprocessor Systems Design
68000 Hardware, Software, and Interfacing.
By Alan Clements (Published by PWS-KENT)
ISBN 0-87150-095-7
The example design is taken from Motorola ECB. It has a seven bit refresh
clock, but more stages could be added,(Thats what I intend to do).
It also covers address multiplexing etc. The book also covers details of
other 68000 systems design.
--
,Kenneth.
K.Cameron@uk.ac.edinburgh kenneth@uk.ac.cs.tardis
"I'll think of something funny sometime, I promise."