ARTABAR@MTUS5.BITNET (03/18/90)
How many bits wide are the address and data buses on the 68030 and on the RAM/SIMMs used by it? I know its a 32-bit machine, but, I know that the 80386, although its a 32bit machine still uses good old-fashioned 8bit RAM. Also...how many clock cycles does a read/write (to RAM) take? Thanx much... Andy
daveh@cbmvax.commodore.com (Dave Haynie) (03/20/90)
In article <90076.195541ARTABAR@MTUS5.BITNET> ARTABAR@MTUS5.BITNET writes: >How many bits wide are the address and data buses on the 68030 and on the >RAM/SIMMs used by it? I know its a 32-bit machine, but, I know that the >80386, although its a 32bit machine still uses good old-fashioned 8bit RAM. Most modern microprocessors need individual byte addressing, regardless of the bus width. This goes along with the programming model that claims 1 address location corresponds to 1 byte. The actual memory you'll find connected to a 68030 is going to depend on the memory subsystem more than anything. I've build 68030 memory systems generally with 256K x 4 or 1Meg x 4 DRAMs, though anything in a "x 8" package, such as a SIMM, would work just as nicely. There isn't a great movement to building DRAMs in "x 8" or larger packages just yet, since most machines are byte-addressed, those that aren't can still use byte wide (or smaller) memories, more data pins make packages larger, and at least until 4 meg density parts start costing less-per-bit than 1 meg density parts, there's not much need for wider data buses -- you're not building cheap, low memory machines with the expensive parts. >Also...how many clock cycles does a read/write (to RAM) take? The minimum 68030 memory cycle runs in two clocks. There's also a burst cache fetch cycle which will get four longwords in five clocks. Most DRAM systems don't run quite so fast, however. The typical 25MHz 68030 PC machine (Amiga, Apple, NeXT) is doing a basic read in about five clocks, sometimes with one or two clock burst cycles as well, from 80-100ns DRAM. Most of the 68030 Workstation machines (HP, Apollo, Sony) have external cache that goes at full speed to external memory, and this external memory may be interleaved to hide the RAS precharge time when possible. >Thanx much... >Andy -- Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Too much of everything is just enough