garlick@csuchico.edu (Jim Garlick) (04/07/90)
In my 68010 manual, I'm having a hard time finding where it says how to use interrupt autovectoring. On the 030 and 040, you pull the AVEC* line, right? What do you do on the 010 and 020? I'd like to avoid handling an interrupt acknowledge cycle at all, if possible.
byron@python.gatech.edu (Byron A Jeff) (04/08/90)
In article <1990Apr07.090036.26347@csuchico.edu> garlick@csuchico.edu (Jim Garlick) writes:
-In my 68010 manual, I'm having a hard time finding where it says
-how to use interrupt autovectoring. On the 030 and 040, you pull
-the AVEC* line, right? What do you do on the 010 and 020? I'd
-like to avoid handling an interrupt acknowledge cycle at all,
-if possible.
Real simple. Just assert the VPA* line on the processor during the
interrupt acknowledge cycle and it will autovector to the appropriate vector.
Be sure that DTACK* does not get asserted during the interrupt acknowledge
cycle. (That info is for 68000, 008, 010. I'm not sure about 020).
Now a question. Does anyone know a source for MCM68H34 dual port static
RAMS? I'm building a MIDI project with 3 processors and want to use
the RAM for interprocessor communication. Seems almost perfect except
it only has 256 bytes. Any leads on another chip with dual port static
rams would be appreciated.
THANKS,
BAJsrg@quick.COM (Spencer Garrett) (04/09/90)
In article <1990Apr07.090036.26347@csuchico.edu>, garlick@csuchico.edu (Jim Garlick) writes: > In my 68010 manual, I'm having a hard time finding where it says > how to use interrupt autovectoring. On the 030 and 040, you pull > the AVEC* line, right? What do you do on the 010 and 020? I'd > like to avoid handling an interrupt acknowledge cycle at all, > if possible. Can't avoid it. The best way I've found to handle this problem is to make sure that the last 7 words of the physical address space are in RAM or ROM and then put the autovector numbers there. If you don't mind a bit of hardware, the a single '244 or '245 on the low byte will do (selected by fc=111).
applix@runxtsa.runx.oz.au (Andrew Morton) (04/10/90)
In article <1990Apr07.090036.26347@csuchico.edu>, garlick@csuchico.edu (Jim Garlick) writes: > In my 68010 manual, I'm having a hard time finding where it says > how to use interrupt autovectoring. On the 030 and 040, you pull > the AVEC* line, right? What do you do on the 010 and 020? I'd > like to avoid handling an interrupt acknowledge cycle at all, > if possible. When the 68000/010 recognises a pending interrupt it puts the level of the interrupt out on a1-a3 and puts FC0, FC1 and FC2 high and asserts /AS. Under these circumstances external hardware must assert (lower) the CPU's /VPA signal. This will cause autovectoring. If the system does not have a mix of vectored & non-vectored interrupt sources you can simply decode FC0-2 high and /AS asserted to drive /VPA low.
normt@cbnewsc.ATT.COM (Norman R Tiedemann) (04/11/90)
In article <1990Apr07.090036.26347@csuchico.edu>, garlick@csuchico.edu (Jim Garlick) writes: >> In my 68010 manual, I'm having a hard time finding where it says >> how to use interrupt autovectoring. On the 030 and 040, you pull >> the AVEC* line, right? What do you do on the 010 and 020? I'd >> like to avoid handling an interrupt acknowledge cycle at all, >> if possible. > >Can't avoid it. The best way I've found to handle this problem is >to make sure that the last 7 words of the physical address space >are in RAM or ROM and then put the autovector numbers there. If you >don't mind a bit of hardware, the a single '244 or '245 on the >low byte will do (selected by fc=111). This is not correct! It is easy to do on the 68000 or 68010. I have designed a couple of processor boards with autovectoring using 68010. It is described in the section dealing with M6800 interfacing (6.3 in my hardware manual) The description is: During an interrupt acknowledge cycle while the processor is fetching the vector, if VPA is asserted (0) the MC68010 will assert VMA and complete a normal M6800 read cycle as shown in Figure 6-4. The processor will then use an internally generated vector that is a function of the interrupt being serviced. This process is known as autovectoring. The seven autovectors are vector numbers 25 through 31 (decimal). Basically what this means is you NAND together FC0, FC1, FC2, and AS(inverted), and feed this output into the VPA input on the processor. So only when all three function control lines are high (CPU space) and the address strobe is low (valid cycle) will the VPA signal be activated, this is the code for the 68010 (and 68000) to do autovectoring. It is completely there, but I agree that the description in the manual is not in an obvious place at all. Hope this helps. Norm Tiedemann AT&T Bell Labs IH 2G-419 att!ihlpy!normt 2000 Naperville Rd. normt@ihlpy.att.com Naperville, IL 60566 -- Norm Tiedemann AT&T Bell Labs IH 2G-419 att!ihlpy!normt 2000 Naperville Rd. normt@ihlpy.att.com Naperville, IL 60566