chrisk@creto.Central.Sun.COM (Chris Kottaridis [Colorado Springs SE]) (06/28/90)
I have a 68010 based computer and would like to run 68020 executables on it. I am investigating the possibility of pointing the illegal instruction vector to a routine that will attempt to emulate 020 user mode instructions that the 010 doesn't have. I don't need to try and emulate 020 supervisory instructions. Before I get in to this too far I thought I'd check with this group to get some feedback on how ludicrous this would be to do. On the outside chance that this has been done any pointers to publicly available source to get it done would be helpful. Thanks Chris Kottaridis (chrisk@sunpike.Central.Sun.COM)
chrisj@netcom.UUCP (Christopher T. Jewell) (06/29/90)
In article <286@texsun.Central.Sun.COM> chrisk@creto.Central.Sun.COM (Chris Kottaridis [Colorado Springs SE]) writes: >I have a 68010 based computer and would like to run 68020 executables >on it. I am investigating the possibility of pointing the illegal >instruction vector to a routine that will attempt to emulate 020 >user mode instructions that the 010 doesn't have. I don't need to >try and emulate 020 supervisory instructions. Before I get in to >this too far I thought I'd check with this group to get some feedback >on how ludicrous this would be to do. On the outside chance that >this has been done any pointers to publicly available source to >get it done would be helpful. It's not the opcodes that get you, it's the addressing modes which were added in the '020 that make the job impossible. For example, suppose your program uses the '020 instruction add.l disp16(a1,d2.l*4),d0 The opcode word specifies indexed addressing, and the extension word looks like this in bits: 0 010 1 10 1 0 0 10 0 000 D 2 L scale*4 format BS IS 16-bit disp no indirection This is followed by a third word which contains the 16-bit displacement. However, a 68010, not knowing about the extended forms of indexing, will ignore the format bit and the scale bits, treat the rightmost 8 bits of the extension word as a displacement of 32, executing the instruction as add.l 32(a1,d2.l),d0 and will treat the 16-bit displacement field as the opcode of the next instruction. In brief, you're Simply Out of Luck. Sorry. -- Chris (Christopher T. Jewell) chrisj@netcom.uucp apple!netcom!chrisj