henry@ginger.sri.com (Henry Pasternack) (09/04/90)
I'm still looking for some detailed advice on DRAM memory system design. Here's another question: As I understand it, the 68030 allows cache-burst access from arbitrary long word addresses. This means that there is no guarantee that a cache burst will begin and end within the same page. The implication is that the memory controller must check for page access and terminate the cache-burst access early if necessary. This is something of a nuisance in a nibble-mode memory where the column address is only available internal to the DRAM. It's even a nuisance with fast page-mode DRAM's (but a necessary one). Is there someone out there who can describe to me in some detail the tradeoffs involved in selecting nibble-mode or fast page mode DRAM's for application with the 68030? I'm not looking for a beginners tutorial, but some detailed information on real applications to help speed my learning process. Thanks a lot. -Henry
bryce@cbmvax.commodore.com (Bryce Nesbitt) (09/04/90)
In article <15852@unix.SRI.COM> henry@ginger.sri.com (Henry Pasternack) writes: > >...Here's another question: > > As I understand it, the 68030 allows cache-burst access from >arbitrary long word addresses. This means that there is no guarantee >that a cache burst will begin and end within the same page. Not quite. The 68030 will *start* a cache-burst at an arbitrary address, then fill in the the remainder of the aligned quad-longword. You might see the following: $XXXXXX08 -> First Fetch $XXXXXX0C -> Second Fetch $XXXXXX00 -> Third Fetch $XXXXXX04 -> Fourth Fetch The 68030 starts with the longword it actually wanted, then proceeds forward to the next longword. After reaching the end it wraps back to backfill the remainder of the cache line. -- |\_/| . "ACK!, NAK!, EOT!, SOH!" "Lawyers: America's untapped export market." {X o} . Bryce Nesbitt, Commodore-Amiga, Inc. (") BIX: bnesbitt U USENET: bryce@commodore.COM -or- uunet!cbmvax!bryce
daveh@cbmvax.commodore.com (Dave Haynie) (09/07/90)
In article <15852@unix.SRI.COM> henry@ginger.sri.com (Henry Pasternack) writes: > > As I understand it, the 68030 allows cache-burst access from >arbitrary long word addresses. This means that there is no guarantee >that a cache burst will begin and end within the same page. Actually, there is. While the first cycle in a burst mode fetch can start on any address, the logical burst address wraps around. So a burst cycle always addresses a single quadlongword aligned quadlongword, it just starts at any longword within that quadlongword. >The implication is that the memory controller must check for page access >and terminate the cache-burst access early if necessary. This is something >of a nuisance in a nibble-mode memory where the column address is only >available internal to the DRAM. No, actually, the 68030 burst cycle exactly matches the nybble mode DRAM cycle -- your first address is supplied, the next three are assumed to be increments, modulo 4, from the first address. >It's even a nuisance with fast page-mode DRAM's (but a necessary one). With page mode or static column memories, you'll have to create low order addresses A2 and A3 for the last 3 cycles in the fetch, but you're guaranteed to stay on the page. > Is there someone out there who can describe to me in some detail >the tradeoffs involved in selecting nibble-mode or fast page mode >DRAM's for application with the 68030? I'm not looking for a beginners >tutorial, but some detailed information on real applications to help >speed my learning process. Nybble-mode memory is much easier to use, but since nybble mode parts are generally available only in "x1" packages (which does kinda make sense), your minimal memory chunk turns out to be 4 Megabytes using 1 Meg x 1, or 16 Megabytes using 4 Meg x 1. For the PRAM/SCRAM system, you can use x4 parts for a minimal memory chunk of 1 or 4 megs, using corresponding memory denisties. But there's more overhead in the control logic, and in general, page or static column cycles are quite as fast as nybble cycles, so you may end up with an extra burst cycle wait state in the PRAM/SCRAM case. >-Henry -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Get that coffee outta my face, put a Margarita in its place!