jstearns@draco.unm.edu (Slix) (10/10/90)
I am seeking information on how to turn the 68020's Instr cache off
and on via hardware. The only literature I have been able to find says
that there is a cache disable pin, but not how to use it. Does anyone
know exactly how this pin is used or where to find specs?? I have been told
that the MC68020 user's manual does not have this info. (hard to believe...)
Thanks for ANY help!!
-Jason
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-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-phil@mcdcup.UUCP (Phil Weinberg SPS) (10/10/90)
In article <1990Oct9.184632.18064@ariel.unm.edu> jstearns@draco.unm.edu (Slix) writes: >I am seeking information on how to turn the 68020's Instr cache off >and on via hardware. The only literature I have been able to find says >that there is a cache disable pin, but not how to use it. Does anyone >know exactly how this pin is used or where to find specs?? I have been told >that the MC68020 user's manual does not have this info. (hard to believe...) The "Cache Disable" pin (notCDIS) is discussed on pages 5-8,5-9, and 6-3 of the 68020 Users Manual - Motorola P/N MC68020UM/AD REV 3.It is also shown on pages 3-97 and 3-98 of the M68000 Family Reference Manual - Motorola P/N FR68K/D. As mentioned in the refrences the usual use of this disable pin is to allow external hardware (emulators) to be able to monitor the processor's opration on a cycle by cycle basis without getting faked out by what is happening in the cache. I'm sure that someone can find some reason to dynamically enable and disable the on-board cache, but it would not normally be used in this mode. Usually the cache is either enabled or disabled and left that way until some event, such as an emulator trigger, would require a change. -- << Usual Disclaimer >> Phil Weinberg @ Motorola Semiconductor, Sunnyvale, CA 94086-5395 UUCP: {hplabs, mot,} !mcdcup!phil Telephone: +1 408-991-7385
bryce@cbmvax.commodore.com (Bryce Nesbitt) (10/11/90)
In article <9089@mcdcup.UUCP> phil@mcdcup.UUCP (Phil Weinberg SPS) writes: >In article <1990Oct9.184632.18064@ariel.unm.edu> jstearns@draco.unm.edu (Slix) writes: >The "Cache Disable" pin (notCDIS) is discussed on pages 5-8,5-9, and >6-3 of the 68020 Users Manual - Motorola P/N MC68020UM/AD REV 3.... > >I'm sure that someone can find some reason to dynamically enable >and disable the on-board cache, For a 68030, dynamic use of the cache is standard. I/O registers assert CIIN (cache inhibit in) to prevent read data from getting cached. The 68030 has a problem, however, with writes in WA mode. Longword writes to longword aligned addresses allocate a valid entry in the data cache even if the hardware asserts CIIN. Without an MMU you are screwed. So: Read from register (no problem, CIIN works) Write long to register (valid entry in D-cache) Read from register (byte, word or long). Boom. Stale data. Could a system play a game with CDIS to work around the above problem? On _read_ of the IO space both CIIN and CDIS would be asserted. This would prevent the 68030 from using the stale data it got in step 2. -- |\_/| . "ACK!, NAK!, EOT!, SOH!" "Lawyers: America's untapped export market." {X o} . Bryce Nesbitt, Commodore-Amiga, Inc. (") BIX: bnesbitt U USENET: bryce@commodore.COM -or- uunet!cbmvax!bryce
michael@mcdchg.chg.mcd.mot.com (Michael Bodine) (10/11/90)
Slix (jstearns@draco.unm.edu) writes: > I am seeking information on how to turn the 68020's Instr cache off > and on via hardware. The only literature I have been able to find says > that there is a cache disable pin, but not how to use it. Does anyone > know exactly how this pin is used or where to find specs?? I have been told > that the MC68020 user's manual does not have this info. (hard to believe...) Yes...a RIDICULOUS assertion! My 020 manual, MC68020UM/AD REV 2, available from Motorola Semiconductor or from your nearest good (technical) bookstore, has section 5.10.1 describing the cache disable pin (it's CDIS*, active low) and refers you also to 6.1 On-Chip Cache Organization and Operation for a description of cache operation, and to 11 Application Information for a description of how this signal is used to assist emulator operation and debugging. -- [ Michael Bodine, michael@chg.mcd.mot.com, Dial: (708) 576-7840, FAX: x8875 ] [ Motorola MCD; Loc IL38; 1100 Woodfield; Suite 334; Schaumburg, Il 60173 ]
phil@motaus.sps.mot.com (Phil Brownfield) (10/15/90)
In article <15052@cbmvax.commodore.com> bryce@cbmvax.commodore.com (Bryce Nesbitt) writes: > >For a 68030, dynamic use of the cache is standard. I/O registers >assert CIIN (cache inhibit in) to prevent read data from getting cached. > >The 68030 has a problem, however, with writes in WA mode. Longword writes >to longword aligned addresses allocate a valid entry in the data cache even >if the hardware asserts CIIN. Without an MMU you are screwed. Are you avoiding the MMU because you don't need address translations? Describe your I/O space as cache inhibited with a Transparent Translation register. The TTx registers still function while address translations are disabled. See 030 User's Manual sections 9.3 and 9.7.3. >Could a system play a game with CDIS to work around the above problem? The difficulty with CDIS is that its timings are not specified with respect to bus cycles. -- Phil Brownfield phil@motaus.sps.mot.com {cs.utexas.edu!oakhill, mcdchg}!motaus!phil Speaking for myself, not my employer
valentin@cbmvax.commodore.com (Valentin Pepelea) (10/17/90)
In article <1990Oct15.145619.18065@motaus.sps.mot.com> phil@motaus.sps.mot.com (Phil Brownfield) writes: > > Are you avoiding the MMU because you don't need address translations? > Describe your I/O space as cache inhibited with a Transparent Translation > register. The TTx registers still function while address translations > are disabled. See 030 User's Manual sections 9.3 and 9.7.3. The I/O space on our computers, the Amiga series - all models, is located in the upper portion of the lower 16 Meg. Within that 16 Meg space, the first 2 megabytes are used by CHIP ram, memory accessible by the graphics coprocessors. We want that part cache inhibited. The top megabyte is reserved as ROM space. That part we want cached. I/O space is located around B000000, while most of the rest is inhabited by extra RAM cards and I/O cards. So the use of the TTx registers would not help at all. Valentin -- The Goddess of democracy? "The tyrants Name: Valentin Pepelea may destroy a statue, but they cannot Phone: (215) 431-9327 kill a god." UseNet: cbmvax!valentin@uunet.uu.net - Ancient Chinese Proverb Claimer: I not Commodore spokesman be