jlehmann@wpi.WPI.EDU (Jonas A. Lehmann) (11/16/90)
Hi, We are currently developing a debugger for embedded systems running on a PC-AT with the embedded system being a MC68008 based machine. Our problem is trying to implement single stepping. We have, or seem to have, no problems single stepping over normal instructions but WHAT HAPPENS IF... Trace-Bit is set and we begin executing. The instruction that follows causes a DIVIDE BY ZERO EXCEPTION. What specifically happens with the order in which these exceptions are processed and what happens with the PC,SR? We Assume the Exception Handling routines just do an RTE. Also, if one exception is pending during another what is the easiest way to check this and to determine which one is pending? Please email any info to Jonas Lehmann - jlehmann@wpi.wpi.edu Jeff Kohler - jkohler@wpi.wpi.edu Thank you ...
mcmahan@netcom.UUCP (Dave Mc Mahan) (11/17/90)
In a previous article, jlehmann@wpi.WPI.EDU (Jonas A. Lehmann) writes: >Hi, >We are currently developing a debugger for embedded systems running on a >PC-AT with the embedded system being a MC68008 based machine. > >WHAT HAPPENS IF... > >Trace-Bit is set and we begin executing. The instruction that follows causes >a DIVIDE BY ZERO EXCEPTION. What specifically happens with the order in which >these exceptions are processed and what happens with the PC,SR? According to the Motorola Programmers reference manual for the M68000 (document number M68000UM(AD4), fourth edition: Section 4.3.3 MULTIPLE EXCEPTIONS (I'm gonna paraphrase the text now) Exceptions can be grouped according to their occuraqnce and priority. Group 0 exceptions are reset, bus error, and address error. They cause the current instruction being executed to abort and the exception processing to commence within two clock cycles. Group 1 exceptions are trace and interrupt as well as the privledge violations and illegal instructions. These exceptions allow the current instruction to execute to completion, but preempt the execution of the next instruction by forcing exception processing to occur (priv. violations and illegal instructions are detected when they are the next instruction to be executed). Group 2 exceptions occur as part of the normal processing of the instructions. The TRAP, TRAPV, CHK and zero divide exceptions are in this group. For these exceptions, the normal execution of an instruction may lead to exception processing. Group 0 has highest priority, group 2 has lowest. Within group 0, reset has highest, followed by bus error and then address error. Within group 1, trace has priority over external interrupts, which in turn take priority over illegal instruction and privledge violations. Since only one instruction at a time can be executed, there is no prioority in group 2. The priority relation between two exceptions determine which is taken, or taken first, if the condtions arise simultaneously. Therefor, if a bus error occurs during a TRAP, the bus error takes precedence, the TRAP processing is aborted. If an interrupt request occurs during the execution of an instruction while the T bit is asserted, the trace exception has priority, and is processed first. Before instruciton execution resumes, the interrupt exception is also processed and instruction processing commences finally in the interrupt handler routine. A summary of exception grouping and priority is listed in the table below. Group Exception Processing 0 Reset Address Error Exception processing begins within two clock cycles Bus Error 1 Trace interrupt illegal Exception processing begins before next instruction Privlege 2 TRAP,TRAPV, CHK Exception processing started by normal instruction Zero divide execution To answer your original question, I assume that the trace bit is set by the end of the instruction that is used to set it. Since the zero divide takes place after the trace bit is set, the CPU will give you the trace exception first, showing what is about to occur. When you do an RTE, you will resume execution at the divide instruction, it will be processed, you will get the zero divide exception processing, and the trace bit will cause your program to give you yet another exception right before the first instruction of the zero divide exception handling routine. When the trace exception occurs, the CPU will go into supervisor mode (if it isn't already) and will clear the T bit to inhibit any more tracing during your trace exception handler. If you want the old SR, you have to look at the exception stack frame generated by the trace exception. >We Assume the Exception Handling routines just do an RTE. But of course! Is there any other legal way? >Also, if one exception is pending during another what is the easiest way >to check this and to determine which one is pending? You can't really 'pend' exceptions. According to the info above, about the only way you can do this is if you get a bus fault or address error while the CPU is in the middle of processing an exception but before the first instruction of it is executed. In that case, the CPU will politely handle the ambiguity by halting the processor. Use of the Reset button is recommended at this time. ;-) >Jonas Lehmann - jlehmann@wpi.wpi.edu >Jeff Kohler - jkohler@wpi.wpi.edu -dave -- Dave McMahan mcmahan@netcom.uucp {apple,amdahl,claris}!netcom!mcmahan
gcarter@globey.cs.wisc.edu (Gregory Carter) (12/03/90)
Hello Everyone!
Well it looks like I have just a few remaining 1040STe's left, exactly
3 to be exact! So, this is the LAST CALL, once there gone, there gone
FOREVER! These are brand new, never opened out of the box.
These 1040STe's are going for 500 bucks a piece. Thats el cheapo!
If you want one, tell me where to ship it, C.O.D. and you can have a
machine that is easily expandable SIMM memory, stereo sound, 4096 colors!
What an XMAS present, plus you can help me get my money back so I can
pay for school next semester!!!!
I must admit TOO, they are ticking my roomate off since its kinda hard
to store all this shit in my dorm! Its not so bad anymore though, thanks for
those who have bought them, before....!!! :)
Well....must go! Talk to you later.
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Greg Carter |Apple: "We make em at 120 bucks a pop
University Wisconsin - Madison | so you can buy at 50000%
608-264-3622 | markup!" - John Scummey
"Intel SUCKS", 386's can't even add!! |"AFTER ALL WE INVENTED THE WINDOW!!!"
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