rh2y+@andrew.cmu.edu (Russell E. Hoffman, II) (02/10/91)
Just out of sheer curiosity .. What hardware debugging features are implemented on the 68040 (Like single-stepping instructions, breakpoints, that sort of thing)? Thanx in advance... Russell Hoffman rh2y+@andrew.cmu.edu Carnegie Mellon Univ.
floydg@oakhill.sps.mot.com (Floyd Goodrich-HiEnd Product Eng) (02/12/91)
In article <1991Feb10.214320.9974@grebyn.com> ckp@grebyn.com (Checkpoint Technologies) writes: >In article <4bh=bBa00YU6MDQUlr@andrew.cmu.edu> rh2y+@andrew.cmu.edu (Russell E. Hoffman, II) writes: >>Just out of sheer curiosity .. What hardware debugging features are implemented >>on the 68040 ... > >If I may add an item to this query, I hear the 68040 chip has an >on-board debug serial port, and I'm wondering how the chip supports this >port. Of course, I have this ideal of something like "console mode" on >a VAX or Micro-ODT on the LSI-11, where microcode in the chip acts >rather like primitive on-chip emulator support. I suspect it's just a >serial port whose IO control regs are in control-reg space with the >cache control regs etc., and if so I'll just be a little dissapointed. The 68040 has the standard M68000 family debugging hooks: traps, breakpoints, tracing, etc. It also has a number of emulator support pins such as TLNx (Transfer Line # indicate which of the 4 lines in the cache is being modified), PSTx (Processor Status pins), CDIS (cache disable), and MDIS (mmu disable). It also has page programmable User Page Attributes which could be used for many things. The part has all the right hooks in place for debugging and emulators to be hooked up. The 68040 does not have a serial port as such. It implements the JTAG standard allowing board-level debug and a quick check that all the pins are hooked up. (You can do other things with the JTAG features, but I wouldn't classify this as debug support.) Floyd Goodrich Motorola Inc., Austin TX floydg@oakhill.sps.mot.com
phil@motaus.sps.mot.com (Phil Brownfield) (02/14/91)
In article <1991Feb10.214320.9974@grebyn.com> ckp@grebyn.com (Checkpoint Technologies) writes: >If I may add an item to this query, I hear the 68040 chip has an >on-board debug serial port, and I'm wondering how the chip supports this >port. The 040 supports JTAG boundary testing (IEEE 1149.1) and so has a serial port for this function. But JTAG is not anything useful for software debugging. So, perhaps someone said _68340_ and you heard _68040_? All the 683XX processors based on the CPU32 core (including the 340 and 332, among others, but not the 68302) support what's called background mode. Background mode is enabled/disabled at reset time. If enabled, assertion of the BKPT* pin, execution of the BGND instruction, or double bus faults halt instruction execution and cause the CPU32 to enter background mode. Via a serial port, it is possible to read/write address/data/supervisor registers as well as memory, and a few other basic debugger primitives. There are a few non-programming model registers accessible. A couple commands cause instruction execution to resume. The serial interface is more like that of SPI peripherals than that of traditional UARTs. Details can be had in the 68340 User's Manual and the CPU32 Reference Manual. If I say more I'm afraid this may start to sound like a commercial. :-( -- Phil Brownfield phil@motaus.sps.mot.com {cs.utexas.edu!oakhill, mcdchg}!motaus!phil Speaking for myself, not my employer.