henry@ginger.sri.com (Henry Pasternack) (02/14/91)
Hi. I'm designing a 68030-to-DRAM interface using 60 nS fast page-mode memory. I've been trying to choose an integrated memory controller, but each chip I've looked at seems to have some fatal flaw. I thought the 74F1763 would do the trick, but then I found what looks like a problem. Maybe someone can help me resolve the following question which concerns refresh arbitration during page- mode accesses. I intend to support both cache burst and non-cache burst page mode DRAM accesses. The 74F1763 has a PAGE input which causes RAS to be asserted continuously during page-mode accesses. During lengthy page-mode accesses, refresh requests are logged internally (up to 128) and handled in a burst following the end of the access. Well, what happens if the CPU loops in page for more than 128 refresh requests? The 74F1763 doesn't have an external refresh request pin, so there's no way to find out a refresh request has been missed. There is a memory grant (GNT) signal which is used to indicate the result of refresh/access arbitration. It would be nice if the 74F1763 would deassert GNT during a burst access upon the overflow of the refresh logger, but I don't think it can do that. Does anyone have any additional information on this topic? Enquiring minds need to know. Thanks. -Henry
israel@mitisft.Convergent.COM (Paul Israel) (02/15/91)
In article <21198@unix.SRI.COM> henry@ginger.sri.com (Henry Pasternack) writes: > > Hi. I'm designing a 68030-to-DRAM interface using 60 nS fast >page-mode memory. I've been trying to choose an integrated memory >controller, but each chip I've looked at seems to have some fatal >flaw. I thought the 74F1763 would do the trick, but then I found >what looks like a problem. Maybe someone can help me resolve the >following question which concerns refresh arbitration during page- >mode accesses. > You know, I keep trying to find the ideal DRAM controller myself, but I never seem to find something that quite fits the bill. There always seems to be one essential feature or another missing, so over the years I've just bitten the bullet and implemented them discreetly, using PALs or miscrosequencers to control them, muxes with high driver capability, a counter for refresh timing, and DRAMs with built-in address counters for CAS-before-RAS refresh cycles. It may seem like a lot of parts next to an integrated solution, but it does have the advantage of allowing you to fine-tune the performance for whatever specific system configuration you're working with. It also allows you to implement precisely the features you need, without worrying about whatever extra baggage comes with the integrated solution. If you're feeling really ambitious, you could try sticking the discreet solution into an ASIC like a Xilinx chip or something. This would help reduce your part count if space is a problem. Hope this was helpful. -- Paul Israel Renegade Systems, 434 South Bernardo Ave, #2 Sunnyvale, CA 94086 Disclaimer: "Who, me? I wasn't even there!" ctnews!mitisft!hamster!israel