joeo@tinton.ccur.com (Joe Orost) (03/01/91)
The 68040 documentation states that the FSGLMUL and FSGLDIV instructions are not supported and trap to the OS. However, testing this fact shows that it is incorrect. The instructions perform as specified by the 68882 manual. Their timings seem to be equal to that of FMUL and FDIV. Was this an official change to the architecture, or is it just temporarily implemented in the current chips for some reason? regards, joe -- Full-Name: Joseph M. Orost Email: joeo@tinton.ccur.com Phone: (908) 758-7284 Fax: (908) 758-7113 US Mail: MS 322; Concurrent Computer Corporation; 106 Apple St Tinton Falls, NJ 07724