panisset@thunder.mcrcim.mcgill.edu (Jean-Francois Panisset ) (04/12/91)
I have the MC68020 Third edition documentation (is there a newer one?),
and I have found what appears to be conflicting information about
the HALT* signal. In section 5.9.2, the signal is descibed in the following
way:
"The halt signal indicates that the processor should suspend bus activity or,
when used with BERR*, that the processor should retry the current cycle.
Refer to 7.5 BUS EXCEPTION CONTROL CYCLES for a description of the effects
of HALT* on bus operations."
And in section 5.13, the Signal Summary, HALT* is listed as an input signal.
But in section 7.5.4, "Double Bus Fault", the last line of the first
paragraph reads:
"When a double bus fault occurs, the processor halts and drives the HALT*
line low".
So what is going on? Is HALT* input only or is it input/output? And if
it is input/output, is it an open-collector output?
On a related note, I am interfacing the 68020 to the VTC VIC068 VME ASIC.
Due to the configuration of the ASIC, it is simpler if the HALT* line is
driven low at the same time as the RESET* line is driven low when the
68020 is to be reset. Does this cause a problem? Should I prevent this
from happening?
Thanks in advance to all you 68k gurus out there...
JF
--
Jean-Francois Panisset
INET: panisset@mcrcim.mcgill.ca
panisset@larry.mcrcim.mcgill.edu
UUCP: ...!mcgill-vision!panisset phil@motaus.sps.mot.com (Phil Brownfield) (04/14/91)
In article <1991Apr11.183130.24243@thunder.mcrcim.mcgill.edu> panisset@thunder.mcrcim.mcgill.edu (Jean-Francois Panisset ) writes: >I have the MC68020 Third edition documentation (is there a newer one?), Yes, the Fourth Edition has been available for some time now. >and I have found what appears to be conflicting information about >the HALT* signal. In section 5.9.2, the signal is descibed in the following >way: > >"The halt signal indicates that the processor should suspend bus activity or, >when used with BERR*, that the processor should retry the current cycle. >Refer to 7.5 BUS EXCEPTION CONTROL CYCLES for a description of the effects >of HALT* on bus operations." > In the Fourth Edition, section 5.9.2 reads: "The assertion of this bidirectional open-drain signal indicates that the processor should suspend bus activity or, when used with BERR*, that the processor should retry the current cycle. Refer to 7.5 BUS EXCEPTION CONTROL CYCLES for a description of the effects of HALT* on bus operations. When the processor has stopped executing instructions due to a double bus fault condition, the HALT* line is driven by the processor to indicate to external devices that the processor has stopped". >And in section 5.13, the Signal Summary, HALT* is listed as an input signal. In the Fourth Edition, it is listed there as input/output. In short, both discrepencies you found in the Third Edition have been resolved in the Fourth Edition. >On a related note, I am interfacing the 68020 to the VTC VIC068 VME ASIC. >Due to the configuration of the ASIC, it is simpler if the HALT* line is >driven low at the same time as the RESET* line is driven low when the >68020 is to be reset. Does this cause a problem? Should I prevent this >from happening? I've been told this ought not be a problem. -- Phil Brownfield phil@motaus.sps.mot.com {cs.utexas.edu!oakhill, mcdchg}!motaus!phil