ddyer@hubcap.clemson.edu (Doug) (04/16/91)
Hello, Of the papers I have read, I can't seem to pin down for certain some things about the 68040 on-chip cache. If anyone could help, I would appreciate it. 1) what is the cache-line replacement algorithm? LRU? Random? All I have found was a mention that the DMEMC was responsible for the selection of the line to be replaced. 2) What is the address resolution of the cache? Looking at the diagrams on the cache the bits 9-4 of the page offset are used as an index into the cache, leaving bits 3-0 for block offset (and 11, 10, opt12 are appended to the address translation). The cache is 32 bits (lw) with a dirty bit for each lw, which seems that only a lw may be accessed, but 4 bits (3-0) can access 16 bytes - the line length. Does the IU know what to do with the lw chunk -assuming the cache deals only with lws? If I got it all wrong, set this lost soul on the correct path, please! E-MAIL to ddyer@hubcap.clemson.edu (yeah, another .edu guy) -- Doug Dyer ddyer@hubcap.clemson.edu
ddyer@hubcap.clemson.edu (Doug) (04/16/91)
ddyer@hubcap.clemson.edu (Doug) writes: > The cache is 32 bits (lw) with a dirty bit for each lw, which ^^^^^^^^^^^^^^^ > seems that only a lw may be accessed, but 4 bits (3-0) can > access 16 bytes - the line length. Does the IU know what to I meant to say "The cache LINE is 4 32-bit long words". -- Doug Dyer ddyer@hubcap.clemson.edu