steveh@tasman.cc.utas.edu.au (Steven Howell) (05/19/91)
Cheers Folks
A question I have, that you just may be able to help me out with.
I have been putting together a simple accelerator for our MC68000
Based prototype mini workstation.
The Boards have been completed, but somewhat few months behind schedule, and
I wish to accelerate their processing performace by replacing the 68000
with the now readily avail nice price power house 68000/16 or 68020/25.
The simplicity of replacing the chip at board level crossed my mind, but was
shattered when I realised I had to divide a heap of timing signals to ensure
compatibility with the SCC, Video, Sound and HD/Floppy disk Interfaces.
So, I had an Idea... I am fairly sure of what needs to be done, but somewhat in
doubt. Maybe some one who has had experience with this sort of interface could
help me.
I wish to send a Bus request (-BR) signal to processor, so that it will release
the CPU, to another CPU. Namely the faster 68000 or 68020.
I understand that (according to my motorola reference manuals) if i send a
(-BR), it will accept, and issue a bus grant signal (-BG), indicating the cpu
has released the bus to the next bus master requesting it.(when it finishes its
last cycle).
What actually happens to CPU when this condition has been met. Does it go high
impedance, and can another processor replace all signals except clock in this
condition. Can another CPU replace all current I/O and operate without
any clashes at a higher speeds. Is it only the buses (address&data) that are
released to another Bus master. Can i remain permanantly in this state after
invoking it.
Can anyone please help me out on this.
Thanks In Advance
Stevehsteveh@tasman.cc.utas.edu.au (Steven Howell) (05/19/91)
Ok. A few updates. I constructed the unit with success. I can, with ease change CPU's in and out from being bus master, BUT, It will not allow a CPU with a faster (or slower for that matter) clock speed to be interchanged. It wont even allow the main processor to reset and start. For some reason they both have to be the same clock speed. Does anyone know a way around this.. thanks steve h
daveh@cbmvax.commodore.com (Dave Haynie) (06/07/91)
In article <steveh.674638341@tasman> steveh@tasman.cc.utas.edu.au (Steven Howell) writes: >The simplicity of replacing the chip at board level crossed my mind, but was >shattered when I realised I had to divide a heap of timing signals to ensure >compatibility with the SCC, Video, Sound and HD/Floppy disk Interfaces. That's true of most systems. My suggestion would be to get one of the 68000 socket upgrades available commercially. There are a number of these puppies on the market. They generally replace your 68000 with a fast 68020 or 68030. One company producing these is Computer Systems Associates. They sell these in the Amiga and maybe Macintosh markets. I don't have their address handy, but they do advertise in most Amiga magazines. >I wish to send a Bus request (-BR) signal to processor, so that it will release >the CPU, to another CPU. Namely the faster 68000 or 68020. You could do that, but... >I understand that (according to my motorola reference manuals) if i send a >(-BR), it will accept, and issue a bus grant signal (-BG), indicating the cpu >has released the bus to the next bus master requesting it.(when it finishes its >last cycle). The 68000 arbiter works like like this. Your alternate bus master asserts BR*. When it's ready to relinquish the bus, the 68000 returns BG*. As soon your alternate master has BG* and AS*, DS*, and DTACK* are negated, it can assert BGACK*, negate BR*, and proceed to drive the main 68000 bus. This mechanism doesn't let you replace any clocks. >What actually happens to CPU when this condition has been met. Does it go high >impedance, and can another processor replace all signals except clock in this >condition. Basically. >Can another CPU replace all current I/O and operate without any clashes at a >higher speeds. That all depends on what's on your 68000 bus. In general, you can't run things faster, because most systems are designed around a known clock speed. You certainly can't supply a faster clock. You may, depending on the system, be able to run a cycle in fewer clocks than the 68000 normally would (four minimum), but again, that's very system dependent. >Can i remain permanantly in this state after invoking it. You can. However, if your system has other potential bus masters, you'll block them with your speed up board if you do. Unless your system is specifically designed to accept some kind of speedup board, it's probably best to physically replace the 68000 with a socket tower , rather than logically replace the 68000 as a bus master. -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy "This is my mistake. Let me make it good." -R.E.M.