sentinel@killer.UUCP (The Sentinel) (05/12/87)
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Well, I think it's about time for a clarification of my SmartWatch problem.
I've received several letters and one news article telling me that the SW
sits under a RAM and not a ROM. However, I have the version which is
specifically designed to go under a ROM... the number is DS1216E.
Instead of using the data lines for input and output, this one uses the
address bus for input and the data lines for output. Input is performed by
reading it with A2 low and the data bit on A0, and output is performed by
reading it with A2 high and getting the data from DQ0. It uses A14 as a
RESET line, resetting it when the pin is pulled low.
I have checked the pinouts on the SW and the 128 schematic (in the
Programmer's Reference Guide), and all of the pins match. The RESET line
(pin 1 on the chip) is tied to +5V, so that shouldn't be a problem. The
/CE line is tied low, but the SW data sheet says "Either control signal
(/OE or /CE) must transition low to begin and high to end memory cycles ...",
and the /OE pin in the 128 does this.
Also, I am running the access routine from low RAM with interrupts
disabled and no peripheral activity, so there should be no ROM accesses
by the system.
Thanks to those who responded to the first article... I hope this one
explains the problem a bit better.
--TS
--
Rob Tillotson ...ihnp4!killer!sentinel
3922-1 Newport Ave. -or-
Fort Wayne, IN 46805 ...rutgers!unirot!sentinel
(219) 483-2722 (top one preferred)