[sci.electronics] TTL Questions

rpluth@pnet01.CTS.COM (Ron Pluth) (07/17/87)

    I have a couple questions about TTL logic that I hope can be
answered here...

    1.  What's the easiest way to go about interfacing a TTL
output (from, say, a standard S or LS AND gate) to a relay, for
controlling anything from automobile (12VDC) to house (120VAC)
environments?  These are two *different* situations.   I'm look
ing for hardware that can be easily picked up at Radio Shack
(gasp!)... if anyone would even happen to know part numbers from
such equipment, this would also be great.

    2.  I've worked with Schottky and Low-power Schottky logic
chips in the lab, and have seen that a no connection to inputs,
such as a simple AND or OR gate, even sometimes in MUX's and
others, drives the input high.  Is this guaranteed true?   If so,
does it apply to all families (S, LS, CMOS, etc.)?  I'm working
on projects that would be a heck of a lot easier if this were
true.

    Send messages to sci.electronics or directly to me.  Any
information is greatly appreciated!
         		                    Ron Pluth

UUCP: {akgua, hplabs!hp-sdd, sdcsvax, nosc}  | "We are all in the gutter,
      !crash!pnet01!rpluth                   |  but some of us are looking 
ARPA: crash!pnet01!rpluth@nosc.mil           |  at the stars."
INET: rpluth@pnet01.CTS.COM                  |              -Oscar Wilde
USPS: 13704 Celestial Rd.  Poway, CA  92064  |

phd@speech1.cs.cmu.edu (Paul Dietz) (07/17/87)

In article <1395@crash.CTS.COM> rpluth@pnet01.CTS.COM (Ron Pluth) writes:
>    1.  What's the easiest way to go about interfacing a TTL
>output (from, say, a standard S or LS AND gate) to a relay, for
>controlling anything from automobile (12VDC) to house (120VAC)
>environments?  These are two *different* situations.   I'm look
>ing for hardware that can be easily picked up at Radio Shack
>(gasp!)... if anyone would even happen to know part numbers from
>such equipment, this would also be great.

There are about 1 zillion and 12 ways of doing this, but just about all
of them depend upon what sort of relay you want to drive, i.e. what
voltage, and what current on the input. One traditional solution is to
use an open collector device (these are fairly easy to find) with a large
pull-up resistor. Connect this output to the base of some big PNP (Darlington
it, if you like) through some appropriate current limiting resistor. Tie
the emitter to the big plus supply (doesn't have to be the same as the TTL
supply) (oh, and the pull-up should go here to...) and the source to your
relay. Tie the other end of the relay to ground. You should also use a
free wheeling diode (a reverse biased diode in parallel with the coil) to
protect the PNP.

A much easier solution is to use a low current, 5-volt relay. Then almost
any of the serious driver chips can drive it directly.

There are also any number of relay driver chips on the market. They are
more obscure, but almost every major manufacturer makes them.

Even better still, do everything solid state! Especially for the household
AC stuff. RS used to carry a wonderful opto-isolator with a triac output.
I believe it could drive tiny loads directly. However, the way to go is
to use it to drive a big triac. This is VERY cheap, very easy, and opto
isolated to boot! However, it's not good for inductive loads...

>    2.  I've worked with Schottky and Low-power Schottky logic
>chips in the lab, and have seen that a no connection to inputs,
>such as a simple AND or OR gate, even sometimes in MUX's and
>others, drives the input high.  Is this guaranteed true?   If so,
>does it apply to all families (S, LS, CMOS, etc.)?  I'm working
>on projects that would be a heck of a lot easier if this were
>true.

Never, never, never, never, never assume this! This is the quickest way
to get into trouble! Yes, standard TTL floats high by nature, but any
mild strays are enough to glitch it to another state! Generic CMOS doesn't
float either direction, so it makes a wonderful antenna, and it will couple
to the subtlest of strays! Since CMOS power glitches when switching, you'd
like to minimize extraneous switching. This is why you SHOULD tie all inputs
somewhere, even if they're on gates you're not using!

While we're on the subject of glitching, watch out when driving relays! These
can cause a substantial glitch on your power line, which WILL cause eratic
behavior of your logic. The moral of this story is to isolate things the
best you can and use big enough power supplies. If you're not sure how to do
this, ASK!

Hope this is what you were looking for...

Paul H. Dietz
Carnegie Mellon University

jl@fornax.uucp (JL) (07/17/87)

> 
>     I have a couple questions about TTL logic that I hope can be
> answered here...
> 
>     2.  I've worked with Schottky and Low-power Schottky logic
> chips in the lab, and have seen that a no connection to inputs,
> such as a simple AND or OR gate, even sometimes in MUX's and
> others, drives the input high.  Is this guaranteed true?   If so,
> does it apply to all families (S, LS, CMOS, etc.)?  I'm working
> on projects that would be a heck of a lot easier if this were
> true.

     The TTL family logic circuits will float high on
an unconnected input.  Note, however, that it may not
be a wise idea to use this because in a very noisy
environment you could find the floating inputs going
low on occation.  This is very unlikely, but why take
the chance?  I ALWAYS connect  ALL  inputs to an output
or to the appropiate power rail.

    ***BUT***

       This is     NOT     true for CMOS !!!!!!!!!!!!!!!!!!!!!
                   ^^^

     CMOS inputs may, by chance, float high or low depending
on everything from what the rest of the circuit in the IC
package is doing to how much noise is in near-by parts of
the layout.

     Not only that, but an unconnected CMOS input can be
very easily damaged by static discharge!

     Never, NEVER, N E V E R    leave a CMOS input unconnected!
(Unless you want totally unpredictable glitches and burnt out
IC's   :-> )

     By the way, with CMOS circuits, you should really connect
up the inputs of the unused gates in a multi-gate IC too because
they are just as likely to get zapped by static discharges too.
For example, if you are using a 4011 NAND gate and you are using
just 1 ( or 2 or 3 ) of the gates, then the other 3 ( or 2 or 1 )
gates should have their inputs connected either to a power rail
of the output(s) of some other part of the circuit.  Of course
the power rail connection is preferable to connecting to other
parts of the circuit because then you increase the capacitance
of the line and slow the system down.
-- 
Jay-El

jans@tekchips.TEK.COM (Jan Steinman) (07/17/87)

<<<1.  What's the easiest way to go about interfacing a TTL output (from, say, 
a standard S or LS AND gate) to a relay, for controlling anything from 
automobile (12VDC)...>>>

My favorite is TIP120 (?) which is a power darlington.  With just one or two mA 
base current, it will drive 8 (?) or so amps.  Who needs a relay?  Just ground 
the emitter, hook you load between the source and the collector, and drive the 
base through about 4.7k.  You can parallel them for more current if you put an 
anti-current-hog resistor between emitter and ground.  About .1 ohm should do 
-- I simply put 10A fuses in each emitter, which seems to add a suitable 
resistance.

 <<<...to house (120VAC) environments?>>>

Use a MOC2010 (?, available from RS) triac-opto-iso driving either another 
triac of the proper rating, or a relay.  There's an ap note on the back of the 
blister-pack.

<<<2.  I've... seen that a no connection to inputs, such as a simple AND or OR 
gate, drives the input high.  Is this guaranteed true?>>>

I'm afraid I don't understand this at all!

:::::: Software Productivity Technologies    ---    Smalltalk   Project ::::::
:::::: Jan Steinman N7JDB	Box 500, MS 50-470	(w)503/627-5881 ::::::
:::::: jans@tekcrl.TEK.COM	Beaverton, OR 97077	(h)503/657-7703 ::::::

hans@umd5.umd.edu (Hans Breitenlohner) (07/17/87)

In article <1395@crash.CTS.COM> rpluth@pnet01.CTS.COM (Ron Pluth) writes:
>
>    1.  What's the easiest way to go about interfacing a TTL
>output (from, say, a standard S or LS AND gate) to a relay, for
>controlling anything from automobile (12VDC) to house (120VAC)
> ...

One effective way to convert from logic levels (including LS and CMOS)
to power levels appropriate for driving relays is to use VMOS transistors.
Like CMOS logic they do not require any extraneous drive current in either
the 'on' or the 'off' state.  Radio Shack used to carry some, I have not
checked recently.

chrisb@bucket.UUCP (Chris Bradley) (07/19/87)

In article <1395@crash.CTS.COM> rpluth@pnet01.CTS.COM (Ron Pluth) writes:
>
>    I have a couple questions about TTL logic that I hope can be
>answered here...
>
>    1.  What's the easiest way to go about interfacing a TTL
>output (from, say, a standard S or LS AND gate) to a relay, for
>controlling anything from automobile (12VDC) to house (120VAC)
>environments?  These are two *different* situations.   I'm look
>ing for hardware that can be easily picked up at Radio Shack
>(gasp!)... if anyone would even happen to know part numbers from
>such equipment, this would also be great.

Well, it all depends on how much currentthe coil in the relay needs to
activate. I'll assume that your digital output is around 5 volts, and
that your relay coil needs to support at least 3 amps. If you can, use
relay (Cat. # 275-214 - $4.69). Then, you need some sort of transistor
that will support (E) 5 / (R) 150 = (I) 33.3 Ma. The transistor doesn't
have to be very powerful in terms of wattage, so we'll use the NPN transistor
(Cat. # 276-2030 - $.79). Now, connect the collector at +12V. Connect the
emitter to one of the coil leads on the relay. Connect the remaining lead
to ground. Now, connect the base to the output wire of your digital logic
circuit. You can now figure out how to wire the rest of the relay up yourself.
You're looking at about 5 bucks total, but you can cheapen the price if you
need less than 3 Amps. If you don't need that much current, use a smaller
comparable one - There shouldn't be any problem in current handling in the
transistor.

-->Chris
..tektronix!reed!percival!bucket!chrisb

rex@otto.COM (Rex Jolliff) (07/20/87)

Expires:

Sender:

Followup-To:


In article <1008@speech1.cs.cmu.edu> (Paul Dietz) writes:
>In article <1395@crash.CTS.COM> rpluth@pnet01.CTS.COM (Ron Pluth) writes:
>>    1.  What's the easiest way to go about interfacing a TTL
>>output (from, say, a standard S or LS AND gate) to a relay, for
>>...
>...
>A much easier solution is to use a low current, 5-volt relay. Then almost
>any of the serious driver chips can drive it directly.

Shouldn't you shunt the relay with a diode to prevent back-emf spikes??
(I don't exactly remember... It's been a while since I've done something
like this...)

>
>
>Paul H. Dietz
>Carnegie Mellon University

this
is
line counter
food

-- 

Rex Jolliff  (rex@otto.UUCP, {akgua,ihnp4,mirror,sdcrdcf}!otto!rex)
The Sun Newspaper -            |Disclaimer:  The opinions and comments in
Nevada's Largest Daily Morning | this article are my own and in no way
Newspaper                      | reflect the opinions of my employers.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
What happened to our superior space program?

phd@speech1.cs.cmu.edu (Paul Dietz) (07/20/87)

In article <426@bucket.UUCP> chrisb@bucket.UUCP (Chris Bradley) writes:
>In article <1395@crash.CTS.COM> rpluth@pnet01.CTS.COM (Ron Pluth) writes:
>>    1.  What's the easiest way to go about interfacing a TTL
>>output (from, say, a standard S or LS AND gate) to a relay, for
>>controlling anything from automobile (12VDC) to house (120VAC)
>
>Well, it all depends on how much currentthe coil in the relay needs to
>activate. I'll assume that your digital output is around 5 volts, and
                                                   ^^^^^^^^^^^^^^
TTL only guarentees 2.4V! Granted, it is generally higher than this,
but it is significantly less than 5V when drawing any current.

>that your relay coil needs to support at least 3 amps. If you can, use
                 ^^^^
Don't you mean the contacts?

>relay (Cat. # 275-214 - $4.69). Then, you need some sort of transistor
>that will support (E) 5 / (R) 150 = (I) 33.3 Ma. The transistor doesn't
                           ^^^^^^^^^^^^^^^^^^^^^
33.3 mA for a 5 volt relay! This seems too low by a factor of 3! Maybe this
is a "typical" spec, but I sure would be shocked if this worked in 
general! (For that matter, is this a 5V relay?)

>have to be very powerful in terms of wattage, so we'll use the NPN transistor
>(Cat. # 276-2030 - $.79). Now, connect the collector at +12V. Connect the
>emitter to one of the coil leads on the relay. Connect the remaining lead
>to ground. Now, connect the base to the output wire of your digital logic
>circuit...

This circuit is loaded with problems!. First of all, the voltage applied
to the coil when "on" can easily be below 2 volts! This is because the
emitter can't go higher than about .6 volts above the base. In practice,
you might typically get between 2 and 3 volts. Hardly enough to drive
most 5 volt relays.

Next problem is the current. TTL has almost no sourcing capability. I don't
have the spec.s for you transistor, but I doubt beta is much bigger than
100 at even 33 mA. Thus, your poor little gate would have to provide .33 mA.
This is definitely pushing TTL and LSTTL which are only rated at .4 mA.
Given the other fudges, you're well beyond that.

Finally, you provide no protection to the poor little NPN when you shut
off the current in the coil. (This works just like the ignition coil
in a car: you shut off the current, and the voltage shoots way up!)
A free wheeling diode will solve this problem.

As I said in my post, there are about a zillion ways of solving this
problem. But this is not one of them...

Paul H. Dietz
Carnegie Mellon University

collinge@uvicctr.UUCP (Doug Collinge) (07/23/87)

In article <1008@speech1.cs.cmu.edu> phd@speech1.cs.cmu.edu (Paul Dietz) writes:
>In article <1395@crash.CTS.COM> rpluth@pnet01.CTS.COM (Ron Pluth) writes:

>>    2.  I've worked with Schottky and Low-power Schottky logic
>>chips in the lab, and have seen that a no connection to inputs,
>>such as a simple AND or OR gate, even sometimes in MUX's and
>>others, drives the input high.  Is this guaranteed true?  
>Never, never, never, never, never assume this! This is the quickest way
>to get into trouble! Yes, standard TTL floats high by nature, but any
>mild strays are enough to glitch it to another state! 

I read a neato book once by a guy who actually went out and tested things
like this, measured the impedance of wirewrap, found out how many bypass
capacitors you actually need, etc.  He said that open TTL inputs WILL NOT
GLITCH even under the most extreme conditions.  Remember, before you flame,
he actually made circuits and tried it out...  He also pointed out that
you can short one output per package indefinitely for testing purposes
with no harm to the chip - actually pretty handy to know.
-- 
		Doug Collinge
		School of Music, University of Victoria,
		PO Box 1700, Victoria, B.C.,
		Canada,  V8W 2Y2  
		collinge@uvunix.BITNET
		decvax!uw-beaver!uvicctr!collinge
		ubc-vision!uvicctr!collinge

peting@cit-vax.Caltech.Edu (Mark Peting) (07/24/87)

In article <294@uvicctr.UUCP> collinge@uvicctr.UUCP (Doug Collinge) writes:
>I read a neato book once by a guy who actually went out and tested things
>like this, measured the impedance of wirewrap, found out how many bypass
>capacitors you actually need, etc.  He said that open TTL inputs WILL NOT
>GLITCH even under the most extreme conditions.  Remember, before you flame,
>he actually made circuits and tried it out...  He also pointed out that
>you can short one output per package indefinitely for testing purposes
>with no harm to the chip - actually pretty handy to know.
>-- 
As someone who has done many digital projects, I can assure you that
unused TTL inputs sometimes WILL glitch.  It is true that they won't
very often, and sometimes a project will work for days before anything
happens, but sooner or later the assumption that they won't will cause
you hours of debugging looking for a very intermitant problem.
I the author mentioned above may never have tried his test on a large
board with large amounts of S parts, since that is the situation
in which there is the most potential for problems, since the S type
TTL has very fast edge rates that create lots of noise.

Also chips can be damaged by shorting only 1 output.  I have had boards
in which a chip was shorted for some time during debugging, and later
failed while the board was in service.  In fact almost every failure
of my projects that happen months later is in a chip that was abused
this way during debugging.  I have taken to throwing out chips that
I find to have been shorted during debugging to avoid these later
failures.  Also outputs in chips in the high power families like S TTL 
will fail very quickly if shorted to VCC.
----------------
Mark Peting
peting@cit-vax.caltech.edu

ken@rochester.arpa (Ken Yap) (07/24/87)

|I read a neato book once by a guy who actually went out and tested things
|like this, measured the impedance of wirewrap, found out how many bypass
|capacitors you actually need, etc.  He said that open TTL inputs WILL NOT
|GLITCH even under the most extreme conditions.  Remember, before you flame,
|he actually made circuits and tried it out...  He also pointed out that
|you can short one output per package indefinitely for testing purposes
|with no harm to the chip - actually pretty handy to know.

That is comforting to know, but I see no reason to tempt fate
unnecessarily.  One easy way of dealing with spare inputs on N/AND,
N/OR gates is to tie them in parallel to another input.  As opposed to
pulling them high with a resistor to +5V.  Provided you stay within the
load capacity of the driving gate.

CMOS inputs should not be allowed to float, of course.

	Ken

phd@speech1.cs.cmu.edu (Paul Dietz) (07/25/87)

In article <294@uvicctr.UUCP> collinge@uvicctr.UUCP (Doug Collinge) writes:
>In article <1008@speech1.cs.cmu.edu> phd@speech1.cs.cmu.edu (Paul Dietz) writes:
>>In article <1395@crash.CTS.COM> rpluth@pnet01.CTS.COM (Ron Pluth) writes:
>
>>>    2.  I've worked with Schottky and Low-power Schottky logic
>>>chips in the lab, and have seen that a no connection to inputs,
>>>such as a simple AND or OR gate, even sometimes in MUX's and
>>>others, drives the input high.  Is this guaranteed true?  
>>Never, never, never, never, never assume this! This is the quickest way
>>to get into trouble! Yes, standard TTL floats high by nature, but any
>>mild strays are enough to glitch it to another state! 
>
>I read a neato book once by a guy who actually went out and tested things
>like this, measured the impedance of wirewrap, found out how many bypass
>capacitors you actually need, etc.  He said that open TTL inputs WILL NOT
>GLITCH even under the most extreme conditions.  Remember, before you flame,
>he actually made circuits and tried it out...  He also pointed out that
>you can short one output per package indefinitely for testing purposes
>with no harm to the chip - actually pretty handy to know.
>-- 
>		Doug Collinge

What?! I hate to disagree, but I have gotten burned with REAL, HONEST TO
GOODNESS circuits by just this problem. To be exact, I had some D flip-
flops that were clearing themselves at random because I had neglected
to tie the clear input! Yes this was on a protoboard which certainly adds
to the problem, but I still would not sleep nights if I knew I had done
this even on a wirewrap board.

My old boss used to say that each new designer had to "get burned" before
he could really understand that these sorts of things are REAL problems.
Maybe 99 times out of 100 you'll get lucky, but eventually, it WILL get you!

This stuff about shorting an output sure sounds pretty hokey to me.
I guess most (though I doubt all) TTL outputs will survive this, however
I doubt you could reasonably expect the rest of the chip to function
normally while under this abuse. By the way, did you ever wonder why
some static CMOS families have a maximum allowable transition
time spec? When switching, there is a usually
brief time when the gates are essentially shorting V+ and ground. If you
switch too slowly, too much energy must be dissipated, and the part can 
easily fail. Clearly, shorting the output to the wrong rail is worse.

--
Paul H. Dietz                                        ____          ____
Dept. of Electrical and Computer Engineering        / oo \        <_<\\\
Carnegie Mellon University                        /|  \/  |\        \\ \\
--------------------------------------------     | | (  ) | |       | ||\\
"If God had meant for penguins to fly,             -->--<--        / / |\\\  /
he would have given them wings."            _________^__^_________/ / / \\\\-
-- 
Paul H. Dietz                                        ____          ____
Dept. of Electrical and Computer Engineering        / oo \        <_<\\\
Carnegie Mellon University                        /|  \/  |\        \\ \\
--------------------------------------------     | | (  ) | |       | ||\\
"If God had meant for penguins to fly,             -->--<--        / / |\\\  /
he would have given them wings."            _________^__^_________/ / / \\\\-

rpw3@amdcad.AMD.COM (Rob Warnock) (07/28/87)

In article <294@uvicctr.UUCP> collinge@uvicctr.UUCP (Doug Collinge) writes:
+---------------
| I read a neato book once by a guy who actually went out and tested things
| like this,...  He said that open TTL inputs WILL NOT
| GLITCH even under the most extreme conditions.  Remember, before you flame,
| he actually made circuits and tried it out...
+---------------

Then he (whoever this anonymous person was) was very, very lucky, and was
(in my opinion) grossly negligent in recommending such behavior to others!

Yes, on a *small* breadboard on your bench in a quiet (electrically) lab,
you can get away with it. I have. I do, still. But I (see signature below
for a real name you can quote) have also personally been burned very badly
(some 25 years ago) by that sort of thing, in production products. I had a
manager giving me the same sort of stuff, "You don't need to pull those guys
up! Pullups are expensive! The design time to wire them is expensive!", and
I let him intimidate me into saving a few bucks. Of course, when the product
failed in the field, it was my fault! (And those things are *hard* to diagnose!)

In a high-speed, high-power system (and if you think TTL is not high power,
calculate the total instantaneous peak power when you pull all 32 lines of
a data bus from TTL high to low within a few nanoseconds, when the bus has
several hundred pF of load per pin -- we're talking *amps*!), unterminated
inputs *do* pick up trash and cause glitches, *especially* inputs such as
preset/clear on a flip-flop. (Yep! They fail only on "some" data patterns...)

*DO NOT* leave inputs floating on commercial products. (What you do in
your home lab is another thing.) You may find yourself with a product
liability suit otherwise (or a criminal charge, if the circuit fails in
such a way as to harm humans, as in an elevator or an airplane).

For the last 25 years, I have preferred to be safe & sure. As a quick & dirty
rule of thumb, put a 1000 ohm to +5 and tie no more than 10-15 inputs to it.
Use "SIP" packages of several 1k pullups to cheaply & safely terminate all
sucj inputs. Don't use long wires on your pullups (they can pick up noise),
use more pullups instead (closer to the packages being pulled up).

Incidentally, if you are careful to never tie the set and preset inputs
of a flip-flop to the same pullup, you can also win some side-effects in
testability (when using "bed-of-nails" testers), since you can set/clear
groups of flops by pulling down the pullup.  (In fact, a testability engineer
I once worked with wouldn't even let us tie constant-zero inputs to ground,
but made us use a low-ohm resistor, so that the testers could override them
for fault isolation. But that's another story...)


Rob Warnock
Systems Architecture Consultant

UUCP:	  {amdcad,fortune,sun,attmail}!redwood!rpw3
ATTmail:  !rpw3
DDD:	  (415)572-2607
USPS:	  627 26th Ave, San Mateo, CA  94403

jeffj@sfsup.UUCP (J.S.Jonas) (07/28/87)

In article <1395@crash.CTS.COM>, rpluth@pnet01.UUCP writes:
> 
>     I have a couple questions about TTL logic that I hope can be
> answered here...
> 
>     1.  What's the easiest way to go about interfacing a TTL
> output (from, say, a standard S or LS AND gate) to a relay, for
> controlling anything from automobile (12VDC) to house (120VAC)

There is a great device called a Solid State Relay.
Surplus places sell them for about $1 per ampere output rating.
It's an optoisolator and triac in one case,
commonly called 'hocky pucks' because of their black cases
despite their being square.

input is usually 3-15 volts at a few milliamperes.
output controls up to 250 volts AC, 1 to 25 amperes is common.
It's got to be AC for the triac to turn off
(this is touted as a feature 'zero crossing shutoff').
Some can turn off an AC wave in the middle of a cycle.
And I found a few that can handle DC.  (probably use transistors
as the switching element).

I once used my Timex Sinclair as a light sequencer by attaching
an 8 bit latch to SSR's which blinked the lights,
by software control!

	Jeffrey Jonas
	{ihnp4 | allegra} attunix ! jeffj

bill@hpcvlo.HP.COM (Bill Frolik) (07/28/87)

>>    2.  I've worked with Schottky and Low-power Schottky logic
>>chips in the lab, and have seen that a no connection to inputs,
>>such as a simple AND or OR gate, even sometimes in MUX's and
>>others, drives the input high.  Is this guaranteed true?   If so,
>>does it apply to all families (S, LS, CMOS, etc.)?  I'm working
>>on projects that would be a heck of a lot easier if this were
>>true.
>
>Never, never, never, never, never assume this! This is the quickest way
>to get into trouble! Yes, standard TTL floats high by nature, but any
>mild strays are enough to glitch it to another state! Generic CMOS doesn't
>float either direction, so it makes a wonderful antenna, and it will couple
>to the subtlest of strays! Since CMOS power glitches when switching, you'd
>like to minimize extraneous switching. This is why you SHOULD tie all inputs
>somewhere, even if they're on gates you're not using!

CMOS devices with floating inputs can cause both the P- and N-channel devices
to be simultaneously on, resulting in a large continuous current through the 
device.  Other gates in the same package may fail to work properly as a 
result of this internal "short".  You should ALWAYS tie all unused inputs
of a CMOS package either high or low.

Bill Frolik
hp-pcd!bill
Hewlett-Packard Portable Computer Division
Corvallis, Oregon  97330

don@umich.UUCP (Don Winsor) (07/30/87)

In the recent discussion on TTL there seem to be numerous
recommendations to use a series resistor when connecting an unused
input to +5 volts.  This is an unnecessary waste of a resistor, the PC
board space to mount it, and the foil trace to connect it.  Can't we
finally give pullup resistors a decent burial?  Unused inputs should
be connected DIRECTLY to the appropriate (+5 Volt or Gnd) supply rail!

A couple of quotes from the net:
] ... it's generally good practice to use a small
] resistor when you attach any input to a rail.
) ... One easy way of dealing with spare inputs on N/AND, N/OR
) gates is to tie them in parallel to another input.  As opposed
) to pulling them high with a resistor to +5V.  Provided you
) stay within the load capacity of the driving gate.
Neither of these is correct for LS, ALS, or FAST TTL.

From Motorola Schottky TTL Data, Series D, Third Printing, 1983:

    UNUSED INPUTS.  For best noise immunity and switching speed,
    unused TTL inputs should not be left floating, but should be
    held between 2.4 V and the absolute maximum input voltage.

    Two possible ways of handling unused inputs are:

    1.  Connect unused input to Vcc.  LS, ALS, and FAST
        TTL inputs have a breakdown voltage > 7.0 V and
        require, therefore, no series resistor.

    2.  Connect the unused input to the output
        of an unused gate that is forced HIGH.

    CAUTION:  Do not connect an unused LS, ALS or FAST input to
    another input of the same NAND or AND function.  This method,
    recommended for normal TTL, increases the input coupling
    capacitance and thus reduces the ac noise immunity.

If all else fails, read the manufacturers data book.

Don Winsor         Ann Arbor, Michigan
University of Michigan EECS Department
... {ihnp4,msudoc,itivax,umix,symplex,arbortext,m-net,aat}!umich!don

max@zion.berkeley.edu (Max Hauser) (08/09/87)

In article <128@umich.UUCP> don@umich.UUCP (Don Winsor) writes:
>In the recent discussion on TTL there seem to be numerous
>recommendations to use a series resistor when connecting an unused
>input to +5 volts.  This is an unnecessary waste of a resistor, the PC
>board space to mount it, and the foil trace to connect it.  Can't we
>finally give pullup resistors a decent burial?  Unused inputs should
>be connected DIRECTLY to the appropriate (+5 Volt or Gnd) supply rail!


Speaking from a historical point of view, I humbly remind the net of
the excellent reason for including the resistor with pre-Schottky
TTL families. TI went so far as to publish an application note for
the 54/74 series, explicitly admonishing against connecting inputs
to the positive power rail under any circumstances.

The reason is because standard TTL inputs, consisting of emitter
diffusions in an NPN transistor, exhibit typical Zener breakdown
voltages of 5.5 volts. Since standard TTL power supplies can be
5.25 volts within spec, a noise spike of 250 mV on the positive
supply would be enough to break down the input and possibly damage
the chip in the absence of a series resistor. If the Schottky
families (where the inputs are isolated Aluminum-Silicon Schottky
junctions) do indeed have a higher breakdown voltage, information
I don't have at hand, then the resistor is unnecessary (although
still harmless).

Perhaps I am old-fashioned but I prefer stating the justification
both for the original requirement of resistors and the contemporary
waiver of that genuine need, so that people will know the reason why,
not just follow commands.

I should add that one never, of course, uses a resistor in series
with inputs tied to ground, for current-sinking logic such as TTL
families (of all kinds), since the major input current flows in the
"low" state, causing a voltage drop that can cloud the logic "0";
and reverse junction breakdown is not an issue in that case.

Also, one can indeed tie unused logic-gate inputs to used inputs;
the penalty is an increased capacitive load to the preceding stage
(not an increase in "AC noise", since (1) the dominant capacitance
at each gate input by far is from package parasitics, not internal 
to the die and (2) two inputs being driven together causes essentially
the same parasitic capacitive currents to flow in the driven chip
as one input driven, for little real change in the AC noise picture).

Respectfully,

Max Hauser, UC Berkeley EECS Department, IC Design Group

   UUCP: ...{!decvax}!ucbvax!eros!max
   Internet (old style): max%eros@berkeley
   Internet (domain style): max@eros.berkeley.edu

wtm@neoucom.UUCP (08/10/87)

Manufacturers recommend tieing unused inputs to logic level high
via a pull-up mainly for the safety of the chip in electrically
noisy environments.  There are often spikes on Vcc that are
considerably greater than the normal nominal operating voltage.
Exposing the inputs to voltages greater than the votage to the
power supply pin of the chip can stress the input, possibly
shortening the life of the chip.  The pull-up resistor limits the
current when a spike occurs.  A 74704 with the input to one of
the inverters tied low is handy for terminating inputs that need to
float high.-- Although tieing low to a poor ground can endanger the
chip too.  In home brew projects, terminating unused inputs to +5
volts is probably alright, but I wouldn't do it in a piece of
equipment I'm planning to sell to somebody else.  One resistor per
every 10 to 15 unused inputs really isn't asking much.-- If you
have a lot of unused inputs, you probably haven't designed your
equipemnt very well.  If the design is going on a PC boad, the cost
of adding the resistors and traces isn't excessive when amortized
over a production run.

  --Bill

wtm@neoucom.UUCP (08/10/87)

Somebody just pointed out again that I can't type in the last
article I wrote, I mentioned using a "74704" as an active
terminator for unused inputs.  What I meant, of course, was the
normal TTL chip, 7404, a hex inverter.

larry@kitty.UUCP (Larry Lippman) (08/11/87)

In article <647@neoucom.UUCP>, wtm@neoucom.UUCP (Bill Mayhew) writes:
> Manufacturers recommend tieing unused inputs to logic level high
> via a pull-up mainly for the safety of the chip in electrically
> noisy environments.

	There is another reason why I use pull-up resistors for unused logic
level high inputs: it makes it easier to implement post-production design
revisions (since the resistor can be easily removed if necessary, or the
pin simply tied elsewhere in the circuitry if the pin is to be pulled down
to logic low).
	While it is not possible to use such a trick when pins are to be
tied to logic low level, if I anticipate a potential future logic change,
I have been known to pull a pin low by employing an unused negative logic
gate or inverter (whose input is pulled high using a resistor).
	I call the above design technique "ECO-logic". :-)

> One resistor per
> every 10 to 15 unused inputs really isn't asking much.

	I would never do this; either use individual resistors, or tie
the inputs to Vcc if you must - but using a common resistor across a
number of logic elements is an invitation to Transient Trouble.

<>  Larry Lippman @ Recognition Research Corp., Clarence, New York
<>  UUCP:  {allegra|ames|boulder|decvax|rutgers|watmath}!sunybcs!kitty!larry
<>  VOICE: 716/688-1231       {hplabs|ihnp4|mtune|seismo|utzoo}!/
<>  FAX:   716/741-9635 {G1,G2,G3 modes}   "Have you hugged your cat today?" 

john@hpcvlo.HP.COM (John Eaton) (08/11/87)

<<<<
< In the recent discussion on TTL there seem to be numerous
< recommendations to use a series resistor when connecting an unused
< input to +5 volts.  This is an unnecessary waste of a resistor, the PC
< board space to mount it, and the foil trace to connect it.  Can't we
< finally give pullup resistors a decent burial?  Unused inputs should
< be connected DIRECTLY to the appropriate (+5 Volt or Gnd) supply rail!
----------

  I suspect that the real reason that everybody does this is that they all
suspect that the circuit may not work as designed. Having some unused inputs
not tied to a rail is very handy if you have to cut traces and add little 
yellow wires to a board to get it into production.


John Eaton
!hplabs!hp-pcd!john
 

neighbor@csd4.milw.wisc.edu (Jeffrey Alan Ding) (08/12/87)

Question:  Would not having pullups on some of the unused inputs to a buffer
           chip cause the malfunction of the other buffers on the same chip?


I'm using a 74LS244 chip.  It's a low power schoktty tri-state octal driver
chip.  I'm only using 4 buffers on the chip and the other 4 are unused.
Will having the inputs to the unused buffers floating cause the other
buffers to sometimes have wrong output signals???


thanks in advance......

neighbor@csd4.milw.wisc.edu

dje@datacube.UUCP (08/14/87)

In 1976 H.P.  Waltham started using 74LS TTL.   We  recieved a waiver
on the input voltage specs of all LS TTL from T.I.  (our  only LS TTL
supplier at the time)  to apply  up to  +15 Volts  to LS  inputs.  We
needed  this  so  we  could  easily  interface  to  the  HP  designed
state-of-the-art +12V SOS CMOS 16 bit processor (the MCC). So I guess
higher voltages Into  LS is (or was) OK.

 				Dave Erickson
----------------------------------------------
  ------      Datacube Inc. 
 /    /|      4 Dearborn Rd. 
------ |      Peabody, Ma 01960
||  \| |      ihnp4!datacube!dje
||  /|/       Human:(617)535-6644
------        Fax:  (617)535-5643

dave@onfcanim.UUCP (Dave Martindale) (08/17/87)

In article <128@umich.UUCP> don@umich.UUCP (Don Winsor) writes:
>In the recent discussion on TTL there seem to be numerous
>recommendations to use a series resistor when connecting an unused
>input to +5 volts.  This is an unnecessary waste of a resistor, the PC
>board space to mount it, and the foil trace to connect it.  Can't we
>finally give pullup resistors a decent burial?  Unused inputs should
>be connected DIRECTLY to the appropriate (+5 Volt or Gnd) supply rail!

Well, if you read the data book for 7400 TTL carefully, you'll see that
it is *not* recommended to tie inputs to Vcc, and that a pullup resistor
should be used.  The reason is that TTL input transistors may break down
at 5.5V, and there is the possibility that the power supply voltage may
go above that value momentarily during turnon or turnoff.  The resistor
limits the current to a value that will not destroy the transistor.

Now, 74LS parts (and others) use diodes instead of a multi-emitter
transistor, and can withstand 7V, so the resistor is not necessary.

It is safe to omit the resistor only if you know that the input in question
can handle the higher voltage.  A general rule of "no resistors" is not
safe.

>
>If all else fails, read the manufacturers data book.

Good advice indeed.

mjj@aplvax.UUCP (Marshall J. Jose) (08/20/87)

Actually, as I recall the various mfrs discussions & recommendations
regading pullups, the primary point was brought up that pullups
improve the overall circuit noise immunity, and that they are
ESPECIALLY recommended for LS gates.  The rationale here is that
plenty of garbage can frequently be found on the Vcc rails, which
might diddle a gate if its input was tied directly there.  Further-
more, due to the different design of LS gate inputs, they can sink a
whopping amount of current under certain overvoltage conditions.
Anyway, I'll go back & dig up my refs. on the subject so we can
settle this.
				Marshall Jose
				mjj@aplvax.jhuapl.edu

mjj@aplvax.UUCP (Marshall J. Jose) (08/20/87)

Ok -- Signetics says LS can be tied to Vcc with SHORT wires &
adequate decoupling.  However, 74xx's should be pulled up with
1k to 10k resistors.  But wasn't there ever some issue about
stored charge in the base-emitter junction, where sloppy pullups
could slow gate switching times?  Anyway, sorry I spoke before
thinking...				Marshall Jose
					mjj@aplvax.jhuapl.edu

rpw3@amdcad.AMD.COM (Rob Warnock) (08/22/87)

In article <20036@ucbvax.BERKELEY.EDU>, after pointing out quite
correctly that in 7400-series (not 74LS') one must *NOT* tie inputs
to the +5 rail, Max Hauser writes:

+---------------
| I should add that one never, of course, uses a resistor in series
| with inputs tied to ground, for current-sinking logic such as TTL
| families (of all kinds), since the major input current flows in the
| "low" state, causing a voltage drop that can cloud the logic "0";
| and reverse junction breakdown is not an issue in that case.
+---------------

Well... there are times when a resistor to ground makes sense, too.
Notice that any resistor value less than "V_max_0/(I_max_0 * #of_inputs)"
will be fine, as it's no worse than a true gate output would be. For a
7400 TTL single "standard load" input, that's 0.4/.016 = 25 ohms or less.

I once worked with a "producability engineer" who insisted that we *NOT* tie
inputs directly to ground (or to +5) for such things as bus-driver enables
which were "always" on. His reason? When using "bed-of-nails" testers to
diagnose a failing board, by driving that resistor to logic high briefly
he could isolate the bus driver from the bus. "Briefly", because we typically
used 10 ohm 1/10-watt resistors for "pulldowns" (used a lot of Schottky),
and they could only take a brief time at +3.5 volts! ("E-square over R"
gives 1.225 WATT!) But a few microseconds was all the tester needed...


Rob Warnock
Systems Architecture Consultant

UUCP:	  {amdcad,fortune,sun,attmail}!redwood!rpw3
ATTmail:  !rpw3
DDD:	  (415)572-2607
USPS:	  627 26th Ave, San Mateo, CA  94403

henkp@nikhefk.UUCP (Henk Peek) (08/23/87)

In article <18007@amdcad.AMD.COM> rpw3@amdcad.UUCP (Rob Warnock) writes:
|In article <20036@ucbvax.BERKELEY.EDU>, after pointing out quite
|correctly that in 7400-series (not 74LS') one must *NOT* tie inputs
|to the +5 rail, Max Hauser writes:
|+---------------
|| I should add that one never, of course, uses a resistor in series
|| with inputs tied to ground, for current-sinking logic such as TTL
|| families (of all kinds), since the major input current flows in the
|| "low" state, causing a voltage drop that can cloud the logic "0";
|| and reverse junction breakdown is not an issue in that case.
|+---------------
|Well... there are times when a resistor to ground makes sense, too.
|Notice that any resistor value less than "V_max_0/(I_max_0 * #of_inputs)"
|will be fine, as it's no worse than a true gate output would be. For a
|7400 TTL single "standard load" input, that's 0.4/.016 = 25 ohms or less.
                                                         ########	

The (low) input curent of a standard single load 7400 TTL input is 1.6 mA.
The maxium serie R for a single load standard input is 0.4/0.0016 = 250 ohms.

henk peek  ..!seismo!mcvax!nikhefk!henkp.UUCP

rpw3@amdcad.AMD.COM (Rob Warnock) (08/25/87)

In article <192@nikhefk.UUCP> henkp@nikhefk.UUCP (Henk Peek) writes:
+---------------
| >In article <18007@amdcad.AMD.COM> rpw3@amdcad.UUCP (Rob Warnock) writes:
| > |Notice that any resistor value less than "V_max_0/(I_max_0 * #of_inputs)"
| > |will be fine, as it's no worse than a true gate output would be. For a
| > |7400 TTL single "standard load" input, that's 0.4/.016 = 25 ohms or less.
| >The (low) input curent of a standard single load 7400 TTL input is 1.6 mA.
| >The maxium serie R for a single load standard input is 0.4/0.0016 = 250 ohms.
| >henk peek  ..!seismo!mcvax!nikhefk!henkp.UUCP
+---------------

Yup! I blew it! Will the net ever forgive?!?!? Mea culpa, folks...
(That's what I get for not doing the whole thing in millivolts and milliamps.)

But the part about using a 1/10-watt resistor for pulldowns and the guy in
manufacturing who wanted to occasionally zap the pulldowns from a bed-of-nails
tester and needing to use short pulses was right, I just forgot what value
we ended up using for a pulldown.

Let's see if I can do simple arithmetic tonight:

I'm sure it was 1/10-watt (they were *small*), so using R = (V^2)/P, if
the tester pulled up to +5 the resistor would have had to been less than
250 ohm to burn up. A 100 ohm resistor would dissipate 1/10 watt if held
high at 3.2 V (and a bit more if held at 3.6), so maybe I was just off by
a factor of 10 and we were using 100 ohm 1/10-watt pulldowns. (Crosscheck:
100 ohms could pull down 4 mA at 0.4 V, which is two 74S' loads. Yes, I know
an 'S low is 0.5 V...)

So. I dropped a power of 10, but was otherwise reporting true.

Sorry again for the error.


Rob Warnock
Systems Architecture Consultant

UUCP:	  {amdcad,fortune,sun,attmail}!redwood!rpw3
ATTmail:  !rpw3
DDD:	  (415)572-2607
USPS:	  627 26th Ave, San Mateo, CA  94403

king@dciem.UUCP (Stephen King) (08/25/87)

<munch>


I have been designing and building TTL circuits for some time and
I have never experienced any problem with LS, S, ALS, F series
parts with inputs tied high/low WITHOUT resistors. I always
distribute a lot of capacitance around my circuits, so VCC is
not noisy, and with proper power supplies never will be. For
the sake of argument, I scanned some of the schematics I have
for multibus cards built by a prominent manufacturer (who shall
remain nameless). In NO instance does this manufacturer uses pull-
ups. All sorts of things are tied high/low in all sorts of circuits.
I looked at CPU cards, memory boards, video cards, frame grabbers, the
works. These items have functioned flawlessly for about three years
now, as have many of my circuits (the remainder have simply fallen into
disuse). So, there's my $0.02 worth. .......................sjk


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