probst@solaris.ifi.ethz.ch@relay.cs.net (Probst) (02/03/88)
The following document I got from the Zilog distributor here in Switzerland (MOOR AG, Regensdorf). Does anybody know of other bugs ? This document is a list of known bugs on the Z280 silicon, Revision G. ---------------------------------------------------------------------- 1. Possible Cache Corruption This bug happens only when the Z280 is used in the Z80 mode. It can be attributed to the fact that the Z280 is designed as a 16-bit device with its internal logic geared towards the transfer of words instead of bytes. In the Z80 bus mode with the cache enabled, a memory read of word quantity data (not instruction) causes the cache to be updated incorrectly. This happens only if the word data address is even aligned. This is best explained in the following example: The stack pointer (xSP) is pointing to location 1004H. The contents of external memory (not cache) locations 1004H and 1005H are "BB" and "CC" respectively. When a "POP HL" instruction is executed, the problem will exhibit itself. For correct operation, the following events should occur: a) Memory Read Transaction with address "001004" valid at time of address strobe (AS). When read (RD) is asserted, the data bus should contain "BB". Cache location "001004" should be updated to "BB" and validated. Register L should now contain "BB" as well. b) Memory Read Transaction with address "001005" valid at time of address strobe (AS). When read (RD) is asserted, the data bus should contain "CC". Cache location "001005" should be updated to "CC" and validated. Register H should now contain "CC" as well. Due to the errata, the following takes place instead: a) Memory Read Transaction with address "001004" valid asserted at time of address strobe (AS). When read (RD) is asserted, the data bus contains "BB". Cache location "001004" inadvertently gets updated to "10" (contents of A15-A8) instead of "BB". Cache location "001005" gets updated to "BB" instead of "CC". Register L now contains "BB" as well. b) No second Memory Read Transaction takes place externally due to the fact that the cache now has "valid" data at location "001005" and supplies that data to the instruction. Register H now contains "BB" as well. This annomally can be circumvented through any of the following methods: a) Use Z-Bus mode instead of Z80. b) Ensure that word data is odd-aligned. This will force two read cycles to occur in order to fetch the data (Z80-bus mode). c) Ensure that no code resides in the same 16-byte memory space (0-FH) that data resides in (A23-A4 cannot be the same) (Z80-bus mode). d) Disable cache (Z80-bus mode). 2. Burst Mode Memory Transactions (Z-bus mode only) It has been discovered that the burst memory cycle does not function as described when in the X2 and X4 bus clock modes. It does function as specified in the X1 bus clock mode. What happens is that the IE signal behaves as if it were a normal memory access cycle. This should not impact any applications because the burst mode is used for high performance, and the highest performance should be observed with the X1 bus clock mode. ---------- Urs Probst X.400: probst@solaris.ifi.ethz.ch UUCP: probst@solaris.UUCP Mail: Langackerstr. 11, CH-8057 Zuerich Switzerland