[sci.electronics] EDIF Tokenizer

waters@dover.uucp (Mike Waters) (10/11/88)

In article <617@stag.UUCP> trb@stag.UUCP ( Todd Burkey ) writes:
>BTW, hasn't anyone come up with a
>tokenized version of EDIF yet? A tokenizer would be simple to write
>and would reduce most EDIF code that I have seen by an order of
>magnitude (if transmission size is an issue).
>
>  -Todd Burkey
>   trb@stag.UUCP
We have done some preliminary work here and published the results at
the last User Group Workshop. We used SEA's ARC program (Motorola has a
Corporate License for some other work), and got results raning up to 95%
compression (O/P 5% of I/P). We used 8 examples ranging in size from a
four bit counteer (20 gates) to a full blown 70,000 gate design
currently being processed as an ASIC Gate Array. The worst results were
with the smallest files, with a "floor" of around 5000 bytes. 
Your estimate of 90% compression is pretty close to the average we saw
for larger designs. The work is continuing as we get more examples and
should be published next year.

The penalty obviously is that you now have a binary file to transmit
with all the traditional hassles that entails with dissimilar systems.

-- 
Mike Waters                 (for your EDIFication)
Motorola SMART CAD Group - EDIF support
Mesa, AZ   ...!sun!sunburn!dover!waters
          OR   moto@cad.Berkley.EDU

johne@hpvcla.HP.COM (John Eaton) (10/13/88)

<<<
< What I find even harder to believe is that an 'EXAMPLE' edif file
< should take up so much space!
----------
EDIF tends to be a bit large. I saw an example of a program that took a
design from a HP-EGS system into a HP-PCDS system by converting into EDIF.
The sample program started out and ended up as about 2 pages of ascii text
but the intermediate EDIF file was 6 pages long. 



John Eaton
!hpvcla!johne