rtm1@thumper.bellcore.com (Ravi Masand) (12/07/88)
Anyone know what a I2C (I squared C) bus is ?? I've just received a "I2C bus compatible ICs" data book from Signetics/Philips which has a lot of interesting devices (mostly audio/video and telephony) but which does not answer the above question. And if you know what it is, where can I find additional info on it ? Thank You. Ravi Masand Bellcore thumper!rtm1 P.S. I'm posting this for the second time. The first time, apparently, it went nowhere.
fnh@briar.philips.com (Fletcher Holmquist;6483;4.85;$0351) (12/08/88)
In article <1404@thumper.bellcore.com>, rtm1@thumper (Ravi Masand) writes: >Anyone know what a I2C (I squared C) bus is ?? >I've just received a "I2C bus compatible ICs" data book from Signetics/Philips >which has a lot of interesting devices (mostly audio/video and telephony) >but which does not answer the above question. >Ravi Masand >Bellcore >thumper!rtm1 I2C stands for Inter-IC-Communications, and is Philips/Signetics scheme for connecting ICs with a serial bus. It uses two wires (SDA-data, SDL-clock), up to a 100KHz clock, terminated with pull-up resisters to +5v. It uses a master/slave relation for transfers, with arbitration between competing masters. One always wins and the transfer it not corrupted, the loser(s) must retransmit. Addresses are software selectable with most masters, most slave ICs have a few lo-bits that are selected via pins, with the hi-bits fixed (e.g. the PCF8583 clock calender + 256 RAM is addrress as 101000x, where x = 0 or 1). The new Signetics books have the full specs, partial specs are part of the specs for I2C devices themselves. [See the Microprocessor Data Book '88]. If you can't find these, send me mail (the 88 I2C book from Philips is strangely lacking the specs). The idea seems to be to interface DACs, ADCs, I/O expansion ports, time-of-day clocks, small memories (RAM, EEPROM), and specialized radio/tv ICs with a microcontroller. It is also being used with the 68070 processor (a 68000 with I2C, UART, MMU, Timers, ...) to implement cheap (low part count) extensions. The two wire scheme makes it much easier to add components, the 8-wire plus interrupt pain is gone. If you want to play with it, I do have some simple 68000 code examples for driving it. I do not have any 8051 examples, however, and most of the 8-bitters having I2C are of that family. The slave ICs, of course, handle the protocol by themselves. It is possible to emulate I2C using any microcontroller's serial port, but it is not as easy as the dedicated port. -- fletch holmquist robotics and flexible automation fnh@philabs.philips.com philips laboratories (914) 945-6483 345 scarborough road, ny, 10510 -- fletch holmquist robotics and flexible automation fnh@philabs.philips.com philips laboratories (914) 945-6483 345 scarborough road, ny, 10510
matthew@sunpix.UUCP ( Sun NCAA) (12/08/88)
Its an interchip serial communications protocol. Think of it this way. Most
CPUs talk to their chips in a parallel fashion. The more chips there are, the
pins there are, the more board real-estate is consumed to hold the chips. Now
consider the devices you've mentioned. They really don't require the higher
processing speed provided by parallel interchip communications, and they
certainly could use a reduction in board real-estate. Sooner or later someone
had to come up with a way for chips to talk serially. In steps Signetics/Philips
with their "I2C bus" and "I2C bus compatible ICs".
--
Matthew Lee Stier (919) 469-8300|
Sun Microsystems --- RTP, NC 27560| "Wisconsin Escapee"
uucp: {sun, rti}!sunpix!matthew |Bill@ucl-cs.UUCP (12/08/88)
Yep, I used an I2C bus system about 3 yrs ago, so my
recollection is a little vague, but it is a 3-wire
serial data protocol with an arbitration system.
The three lines were CLOCK, DATA, <something else - GND??>
and you could have at least one MASTER device, and several
SLAVE devices. We used only one master, so I never investigated
the multimaster facility (if it existed!), and the protocol
consists of the master looking at the lines to see if they
are floating, and if they are it asserts an address which
corresponds to a particular slave (slaves have the address
hardwired in). If the slave needs data, then this is sent too.
The clock is used to synchronise the data. Then the slave can
reply with some response. The data speed goes up to about
500Kbits/s, I think. The maximum length of the bus line should
not exceed about 2 metres or so because signals are asserted as
LOW=0V, HIGH=Floating->5V.
This is intended as a VERY ROUGH GUIDE!!! The information
above should all be checked up - I did not design any I2C
stuff, I just sent addresses and data to the I2C software that
another guy wrote. The master, in our case, was a 6303
processor and the I2C was controlled by some general I/O lines.
We used it to run a Mullard teletext controller/acquisition chip and a
TV tuner chip - I forget the numbers.
POINTS TO NOTE:
The I2C protocol driver for one master was written in under a
day, so it isn't too difficult.
All device types that are used on the I2C bus will have a
unique address code, which is shown in the data book for the
device. Some (all?) also have another address, selectable by a
pin, which can be used if you want two devices on the bus.
Hope this is of some help, sorry I cannot recall more, but I
don't have any of the design sheets anymore. Have fun!
... Bill
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Bill Witts, CS Dept. * Nel Mezzo del cammin di nostra vita
UCL, London, Errrp * mi ritrovai per una selva oscura
william@cs.ucl.ac.uk * che la diritta via era smarrita.
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