jelynch@hubcap.clemson.edu (james e lynch) (04/09/89)
D
I am working on alpha induced upsets in dynamic random memories. Currently, I am considering alpha strikes on the bit-lines as a mechanism of depositing chargewhich alters the state of the memory cell. I am looking of information on the pre-charging of the bit-line before it is connected to the cell. I am mainly interested in the TMS4256, but will appreciate any information on dRAM architecture and/or timing. Please reply to my bitnet address
jelynch@hubcap.clemson.edu
mark@mips.COM (Mark G. Johnson) (04/10/89)
In article <5044@hubcap.clemson.edu> jelynch@hubcap.clemson.edu (james e lynch) writes: >I am working on alpha induced upsets in dynamic random memories. >Currently, I am considering alpha strikes on the bit-lines as a >mechanism of depositing chargewhich alters the state of the memory >cell. I am looking of information on the pre-charging of the >bit-line before it is connected to the cell. I am mainly >interested in the TMS4256, but will appreciate any information >on dRAM architecture and/or timing. As you probably know, bitline hits are alpha-particle events that don't strike memory cells; they strike bitlines (by definition). Therefore they don't hurt the stored charge in the memory cells. However, it is possible (but rare) for a bitline-hit to confuse the sense amplifier, which then flips the wrong way and thus *refreshes* the wrong data back into the cell. The peculiar mechanism for this is described below. The DRAM timing chain is designed so that several critical events take place in a known order: (A) ... lots of previous things happen not germane to BL hits ... (B) The bitline-to-bitlineBar equilibration transistor is shut off (C) The wordline and dummy wordline are asserted (D) Memory cell data is dumped onto the bitlines (E) The sense-amp latch clock is fired (F) ... and then other things happen after that ... The **only** time that an alpha bitline-hit can possibly affect the readout data (and/or the refresh data) is the time between (B) and (E), the so-called bitline "float time". Before (B), the alpha charge is shared between bit and bitBar so the senseamp is unaffected. After (E) the bitline is actively driven so an alpha strike is swamped by the low-Z and hi-C of the hard-driven bitline. DRAM companies have a neat way of examining this kind of behavior: plot soft error rate versus RAS cycle time. Make sure to take data at both ends of the extreme: Extremely short cycles, and extremely long ones (2-32 milliseconds). You get a "bathtub curve". At long cycle times the SER goes up because the cells need to be refreshed and so are more sensitive. ==> At short cycle times the bitline float-time is a non-negligible <== ==> fraction of the cycle time, and bitline hits contribute to the SER.<== In between, SER is completely determined by cell-hits; bitline hits are negligible. For one 256K dram that I'm familiar with, the bitline float-time is 7 nsec typically. No, it isn't the TI TMS4256. Here's a good paper: D. Segers et al, "Circuit Design Methodologies for the Reduction of Alpha Soft Error Rate", IEDM Technical Digest, December 1983, pp.331-5. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 ...!decwrl!mips!mark (408) 991-0208