dente@s2.uucp (Colin Dente) (03/31/89)
In response to someone's (sorry - I don't recall who) comment about people using the AT bus for anything other than 80x86 boards - well Apollo use it in all their latest 'Personal workstations' (i.e. DN3000, 4000, 3500 & 4500) and it don't seem to do them no harm. It's not used for everything (e.g. memory) - but then do PC maker's never put fast busses for RAM (he asks, thereby displaying 100% lack of knowledge of IBM PCs). I must agree with the original idea - use of this bus *would* give access to loads of cheap peripherals - just so long as nobody suggests it should run MSDOS - I think I'd unsubscribe immediately if that happened!!! This does, however, lead to all sorts of wondering about operating systems and processors - as these are fairly fundamentally inter-related - are we aiming for a cheap unix box? - or is someone going to write a whole new operating system? (offers?). What would people want out of this machine? Apologies for the deranged, meandering stream of thought, I've been here for the last 36 hours, and the screen keeps going out of focus! Colin =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= | Colin Dente | JANET: ECAD@UK.AC.MAN.EE.V1 | | Dept. of Electrical Engineering | ARPA: ECAD%UK.AC.MAN.EE.V1@UKACRL.BITNET| | University of Manchester | UUCP: ...!mcvax!ukc!man.cs.ux!s2!dente | | England | | |-----------------------------------------------------------------------------| | Anybody want to buy a Starfighter?..... Buy an acre of ground, and wait... | =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
sl@van-bc.UUCP (pri=-10 Stuart Lynne) (04/01/89)
In article <5768@ux.cs.man.ac.uk> dente@s2.uucp (Colin Dente) writes: >I must agree with the original idea - use of this bus *would* give access >to loads of cheap peripherals - just so long as nobody suggests it should >run MSDOS - I think I'd unsubscribe immediately if that happened!!! > Just a note that various (Televideo and Zenith comes to mind) PC manufacturers actually manufacture machines that don't really have a motherboard. It is simply a bus, plus power. They implement the CPU on a card allowing you (for example) to upgrade from a 286 to 386 just by adding a processor. Typcially in the larger 386 systems, memory is hooked in via a daughter board or ribbon cable to avoid delay of access of the AT bus. This might be the way to go in developing a low cost hobbyist machine. It does allow access to a large number of very low cost cards. You can have a 10 or 12 slot bus and just plug whatever you want into it. -- Stuart.Lynne@wimsey.bc.ca uunet!van-bc!sl 604-937-7532(voice) 604-939-4768(fax)
byron@pyr.gatech.EDU (Byron A Jeff) (04/01/89)
In article <5768@ux.cs.man.ac.uk> dente@s2.uucp (Colin Dente) writes:
-In response to someone's (sorry - I don't recall who) comment about people
-using the AT bus for anything other than 80x86 boards - well Apollo use it
-in all their latest 'Personal workstations' (i.e. DN3000, 4000, 3500 & 4500)
-and it don't seem to do them no harm. It's not used for everything (e.g.
-memory) - but then do PC maker's never put fast busses for RAM (he asks,
-thereby displaying 100% lack of knowledge of IBM PCs).
I rememered that piece of info about a day after I posted the question.
I used to work on a DN3000 (68020 based unixlike workstation).
-
-I must agree with the original idea - use of this bus *would* give access
-to loads of cheap peripherals - just so long as nobody suggests it should
-run MSDOS - I think I'd unsubscribe immediately if that happened!!!
Just as long as we agree on at base idea.
-
-This does, however, lead to all sorts of wondering about operating systems
-and processors - as these are fairly fundamentally inter-related - are we
-aiming for a cheap unix box? - or is someone going to write a whole new
-operating system? (offers?). What would people want out of this machine?
-
-Colin
Definitly Unix. I'd wait 'til the illustrious Mr. Stallman finishes
GNU. Should be in a year or two right?
Processors: Linear address space, 32 bit (or more) address, data busses,
orthagonal instruction set (for those sick puppies who write device
drivers and other similar ilk is assembly), Virtual memory/paging support.
Fast.
I'd want something that can do real work but that I can have fun tinkering
with both hardware and software. It would be real nice if it didn't
break the bank either.
BAJ
--
Another random extraction from the mental bit stream of...
Byron A. Jeff
Georgia Tech, Atlanta GA 30332
Internet: byron@pyr.gatech.edu uucp: ...!gatech!pyr!byronrzh@lll-lcc.UUCP (Roger Hanscom) (04/04/89)
In <2342@van-bc.UUCP>, sl@van-bc.UUCP (pri=-10 Stuart Lynne) writes: |In article <5768@ux.cs.man.ac.uk> dente@s2.uucp (Colin Dente) writes: | |>I must agree with the original idea - use of this bus *would* give access |>to loads of cheap peripherals - just so long as nobody suggests it should |>run MSDOS - I think I'd unsubscribe immediately if that happened!!! |> | |Just a note that various (Televideo and Zenith comes to mind) PC manufacturers |actually manufacture machines that don't really have a motherboard. It is |simply a bus, plus power. They implement the CPU on a card allowing you (for |example) to upgrade from a 286 to 386 just by adding a processor. ...........details deleted here........... |This might be the way to go in developing a low cost hobbyist machine. It |does allow access to a large number of very low cost cards. You can have a |10 or 12 slot bus and just plug whatever you want into it. The more things change, the more they remain the same! Sounds like the S-100 bus. A nifty idea from the past. Power supply and bus connectors on the backplane -- any board that conforms to the protocol can be swapped into the configuration. What a disaster for the planned obsolescence folks .... they wouldn't be able to sell us a whole new set of hardware every n years. Now, before I get flamed for suggesting such a tacky thing as the S-100 bus, let me say that I realize that it had (has) some serious disadvantages, but the **CONCEPT** was, and is, an excellent one. It worked because of its simplicity and the fact that it was a hobbyist bus, and did not get taken over by the hi-dollar market. Face it, buses like the VME, multi-bus, etc. could never fit this particular niche, not because they are inappropriate, but because the cards for these buses are priced beyond the reach of most of us -- for personal use. -------------------------------------------------------------------------- roger rzh%freedom.llnl.gov@lll-lcc.llnl.gov ucbvax!lll-lcc!freedom!rzh Upstairs, Over a Vacant Lot, Inc.
jimc@iscuva.ISCS.COM (Jim Cathey) (04/06/89)
In article <5768@ux.cs.man.ac.uk> dente@s2.uucp (Colin Dente) writes: >In response to someone's (sorry - I don't recall who) comment about people >using the AT bus for anything other than 80x86 boards - well Apollo use it >in all their latest 'Personal workstations' (i.e. DN3000, 4000, 3500 & 4500) >and it don't seem to do them no harm. It's not used for everything (e.g. >memory) - but then do PC maker's never put fast busses for RAM (he asks, >thereby displaying 100% lack of knowledge of IBM PCs). The PC bus is not very good, especially when it comes to interrupts. Who ever heard of a serious bus that had TTL active-high interrupts!!! (For those who don't know, it means you can't have several boards share an interrupt request line. This is a serious problem with PC's -- they only support 8 interrupts total. For the AT, all they did was add 7 more, and they used most of these up internally to the box. The damned bus is _still_ active-high TTL for interrupts.) PC bus is a lousy choice for the conceptual successor to the S-100. For my 2 cents' worth, they should put the designers of the 8259, 8250, and 765 (8272) chips up against the wall and shoot 'em. Garbage, one and all. +----------------+ ! II CCCCCC ! Jim Cathey ! II SSSSCC ! ISC Systems Corp. ! II CC ! TAF-C8; Spokane, WA 99220 ! IISSSS CC ! UUCP: uunet!iscuva!jimc ! II CCCCCC ! (509) 927-5757 +----------------+ "With excitement like this, who is needing enemas?"
jhallen@wpi.wpi.edu (Joseph H Allen) (04/07/89)
In article <2445@iscuva.ISCS.COM> jimc@iscuva.ISCS.COM (Jim Cathey) writes: >The PC bus is not very good, especially when it comes to interrupts. Who ever >heard of a serious bus that had TTL active-high interrupts!!! (For those who >don't know, it means you can't have several boards share an interrupt request >line. This is a serious problem with PC's -- they only support 8 interrupts >total. For the AT, all they did was add 7 more, and they used most of these >up internally to the box. The damned bus is _still_ active-high TTL for >interrupts.) It makes me wonder if IBM's designers even understand interrupts... I'd even prefer if they had a single interrupts line and polled dispatching. >PC bus is a lousy choice for the conceptual successor to the S-100. I'm not sure about this- there are probably more PC buses out there than any other kind. It all depends on what you mean by "conceptual successor". As I remember the S-100 was pretty lousy too. >For my 2 cents' worth, they should put the designers of the 8259, 8250, and >765 (8272) chips up against the wall and shoot 'em. Garbage, one and all. Did you ever try to program the serial port? You have to set-up and enable _4_ chips. Sure these chips are bad, but IBM is worse by actually _using_ them. And now for my 2 cents' worth: If I had designed the IBM PC bus.... ( :-) it would be something like this: GND 8 pins +5V 8 pins +12V 2 pins -12V 2 pins All on opposing corners so that you can plug boards in backwards. (actually, some kind of transmission line analysis should be done to do this correctly but I'd guess that this would be acceptable for a small bus). RESET* Wire-or, low is active. Maybe I'd replace one of the GND pins with it so that if you plug a board in backwards the system stays reset (and when reset is active, all output gates would be tri-state). D0-D15 Data bus R/W* Direction A1-A23 Address bus BYTE0* Lower byte transfer BYTE1* Upper byte transfer E Main clock. Falling edge is when data is due- this way, E can go through a single NAND gate and connect to a rising edge clock device. The timing at this edge is the most important decider of bus speed so it should be designed to minimize the number of gates E has to go through to interface it with things. Outputs to the data bus should be enabled while E is high (I.E., E low is device disable time) WAIT* All boards should be designed to be synchronous by default yet upgradable. The time between low E edge and high E edge should be checked on each board so that WAIT can be invoked in case the bus speed is increased beyond the speed of the board to stretch E. IRQ0-7* Interrupt requests. No ACK cycle- device holding IRQ down is cleared by software. DMARQ0-7* DMA request lines. Device holding DMARQ low releases when the transfer occures. There, a total of 81 lines so probably an 86 pin connector should be used. Note that this is only meant to be a single processor bus such that the boards need the absolute minimum of hardware to interface to the bus. For multiple bus masters I'd probably add these: WHO0-2 Who owns the bus. BREQ0-7* Request the bus. 7 should use round-robin technique, 1 should have priority for the DMA controller. Request should be placed right after E going low and response on WHO should appear at next E going high so that the owner can take over on the next cycle. LOCK* To prevent ownership change for read/modify/write sequences. Issues to resolve: how to expand the data bus how to interrupt other than the default processor
henry@utzoo.uucp (Henry Spencer) (04/07/89)
In article <2445@iscuva.ISCS.COM> jimc@iscuva.ISCS.COM (Jim Cathey) writes: >For my 2 cents' worth, they should put the designers of the 8259, 8250, and >765 (8272) chips up against the wall and shoot 'em. Garbage, one and all. No, no. Ammunition is expensive. Strangle them. It's slower, too. -- Welcome to Mars! Your | Henry Spencer at U of Toronto Zoology passport and visa, comrade? | uunet!attcan!utzoo!henry henry@zoo.toronto.edu
jkingdon@chinet.chi.il.us (Jim Kingdon) (04/08/89)
jhallen@wpi.wpi.edu (Joseph H Allen) writes: >IRQ0-7* Interrupt requests. No ACK cycle- device holding IRQ down > is cleared by software. >DMARQ0-7* DMA request lines. Device holding DMARQ low releases when > the transfer occures. No, give each slot its one line. And its own address space. Cuts down on the number of pins on the connector and eliminates conflicts between cards. Like the Apple II or NuBus. If each board is also required to have a ROM (I'm unsure about whether this is a good idea) the whole can operate without any configuration at all, the system just knows what all that boards are. Even without a ROM you only have to say "slot 6." Help stamp out DIP switches within our lifetime!
jhallen@wpi.wpi.edu (Joseph H Allen) (04/09/89)
In article <8162@chinet.chi.il.us> jkingdon@chinet.chi.il.us (Jim Kingdon) writes: >jhallen@wpi.wpi.edu (Joseph H Allen) writes: >>IRQ0-7* Interrupt requests. No ACK cycle- device holding IRQ down >> is cleared by software. >>DMARQ0-7* DMA request lines. Device holding DMARQ low releases when >> the transfer occures. > >No, give each slot its one line. And its own address space. Cuts down >on the number of pins on the connector and eliminates conflicts between >cards. Like the >Apple II or NuBus. If each board is also required to have a ROM (I'm >unsure about whether this is a good idea) the whole can operate without >any configuration at all, the system just knows what all that boards >are. Even without a ROM you only have to say "slot 6." Help stamp >out DIP switches within our lifetime! The only prolem I have with this is that each board may have more than one interrupt/dma device. If you are also willing to have requests between multiple devices on each board resolved on board (a la Z80 perhaps) then I agree. If you do this then you probably also want to have vectored interrupts so that the board can indicate which device actually gave the interrupt. Another possibility is to have a single interrup line and have software do the dispatching. This might not effect speed so badly since extremely fast devices would use DMA and the search order in the dispatch poll routine could further indicate device priority. Address space: perhaps we want two buses, a multiple processor/memory bus and a peripheral bus. I don't like the idea of ROM on board since then the boards are forced to work with only one processor type. Oh, minor update: replace BYTE0* and BYTE1* with BYTE0 and BYTE1 (I.E. non-inverting so that they can go into a NAND gate with clock and chip select signals). Also, I nominate Apple-II bus as "best" commonly available bus yet devised. After all, on what other computer have you seen disk controllers which only use 5 TTL chips? (of course, there is Wozniak's power supply problem...).
daveh@cbmvax.UUCP (Dave Haynie) (04/18/89)
in article <1758@wpi.wpi.edu>, jhallen@wpi.wpi.edu (Joseph H Allen) says: > And now for my 2 cents' worth: If I had designed the IBM PC bus.... ( :-) it > would be something like this: [goes on to describe desired PC bus signals] Things also missing: SLAVE* Asserted by a card when it's responding to an address. Each slot has it's own. This means that bus control hardware is capable of detecting when two cards try to respond to the same address. It also lets you do other neat things... Take the stuff you mentioned, the SLAVE signal above, change DMA a little, and you're pretty close to the Amiga expansion bus. Amiga cards also have a mechanism that lets software poll them and figure out how much space they need, then locate them in space required, providing there is enough space left in the area reserved for expansion. > Issues to resolve: how to expand the data bus > how to interrupt other than the default processor If you're starting to think about multiple CPU systems on the bus, you need to consider how to support cache consistency. -- Dave Haynie "The 32 Bit Guy" Commodore-Amiga "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: D-DAVE H BIX: hazy Amiga -- It's not just a job, it's an obsession