[sci.electronics] 6551 ACIA questoin.

mwedel@hobbes.uucp (Mark Wedel) (08/04/89)

  I am doing some programming for this device, but the documentation I have
for it leaves me with one question.

 For the Command register, the documentation for bits 2-3 (the bit numbering
is 0-7) leaves me wanting more information.  Here is the description I
have for it:

2-3 Control transmit interrupt, Request to Send (RTS) level, and transmitter.

 What I want is something that describes what to write to each bit to get
a desired result (send byte, control of RTS, and so forth.)

 Any help appreciated.

 Mark Wedel
 mwedel@antares.Tymnet.Com	!ucbvax!hplabs!oliveb!tymix!antares!mwedel

Ric@cup.portal.com (Richard Knowles Rainbolt) (08/05/89)

According to the Rockwell manual:

Bit #
3   2       Mode

0   0       RTS* high, transmitter disabled
0   1       RTS* low, transmitter interrupt enabled
1   0       RTS* low, transmitter interrupt disabled
1   1       RTS* low, trans interrupt disabled, Transmit Break on TxD.

Hope this helps!
-Ric-
(Ric@cup.portal.com)

matthew@sunpix.UUCP ( Sun Visualization Products) (08/07/89)

 In request for more info on the 6551 ACIA command register, Heres some 
info from data sheets on the 6551.

Command Register:
	Bit 7 6 5  [Parity Control]
	    - - 0  Parity disabled - No parity bit generated. None received.
	    0 0 1  Odd parity received and transmitted
	    0 1 1  Even parity received and transmitted
	    1 0 1  Mark parity sent, receive parity check disabled
	    1 1 1  Space parity sent, receive parity check disabled

	Bit 4      [Echo Control]
	    0      Normal
	    1      Echo (bits 2 and 3 must be zero)

	Bit 3 2    [Transmitter Control]
	    0 0    Transmit Interupt disabled. RTS* = High, Transmitter = off
	    0 1    Transmit Interupt enabled.  RTS* = Low,  Transmitter = on
	    1 0    Transmit Interupt disabled. RTS* = Low,  Transmitter = on
	    1 1    Transmit Interupt enabled.  RTS* = Low,  Transmitter = BREAK

	Bit 1      [IRQ Control]
	    0      IRQ* interrupt enabled from bit 3 of status word.
	    1      IRQ* interrupt disabled.

	Bit 0      [DTR Control]
	    0      Disable receiver and all interrupts. (DTR* high)
	    1      Enable receiver and all interrupts. (DTR* low)


-- 
Matthew Lee Stier                            |
Sun Microsystems ---  RTP, NC  27709-3447    |     "Wisconsin   Escapee"
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