yerazunis@cthulu.dec.com (10/11/89)
In article <5304@shlump.nac.dec.com>, yerazunis@cthulu.dec.com writes... >I've built the following and subjected it to autocorrellation, slicing, >and entropy examination for blocks of 1000 bytes. It never came out >with less than 7.8 bits/byte entropy... > >Take an ordinary NPN transistor. Tie the collector to the base, and then >forward-bias it so you get about a 0.1 mA current through it (this was a 10K >resistor in my application). Lead the connection between the resistor and the >transistor to the - input of an op-amp. Tie the output of the op-amp to (1) a >50K resistor in series with a 10-microfarad capacitor, thence to ground and (2) >directly to the CPU input port. Connect the 50K/10u junction to the + input of >the op-amp. That's it. (this, of course, presumes an op-amp that can work >on a +5V single-ended supply. If you don't have one, then buffer the op-amp >output with a CMOS inverter. This makes all the zeroes into ones, and all >the ones into zeroes, but since the bits are supposed to be random you'll >probably never notice. Aw, shoot. As mark%obiwan.mips.com@mips.com and others have pointed out, I flipped a bit there. Where I said + input I should have said -, and vise-versa. If built as described, you get either all 1's or all 0's. (the idea is that the transistor-resistor junction will have a few milli- volts of noise on it, and that noise can be amplified to give the random bit stream. The average voltage of that junction (averaged by the 50K/10uF capacitor) provides the decision threshold between 0 and 1. ) Repeating that- the transistor-resistor junction goes to + and the resistor-capacitor junction to the - input of the op-amp. My apologies to the net, and my thanks to those that caught this error. They can stop sending me messages now... :-) -Bill Copyright 1989 William S. Yerazunis (aka Crah the Merciless) All rights reserved, no responsibility taken. "I lifted my uncomprehending eyes to the heavens..."