foperator@tekno.chalmers.se (Daniel Berglund) (11/02/89)
I have a question about the "CAS-before-RAS" refresh mode found in certain DRAMs (specifically, 4464 (64Kx4)). The data sheet states that the chip will generate the row address internally. Does this mean that the only thing I will have to do to keep the memory refreshed is to toggle CAS and RAS with the prescribed timing every once in a while? As I just have spent some hours to design a clever (?) network of counters, gates, buffers etc in order to keep track of the very same row address, this seems a little bit too good to be true. Please tell me that it is. :-) Thanks in advance, -- Daniel Berglund (foperator@tekno.chalmers.se, BITNET: FOP@SECTHF51) Chalmers University of Technology, G|teborg, Sweden
daveh@cbmvax.UUCP (Dave Haynie) (11/03/89)
in article <3056@tekno.chalmers.se>, foperator@tekno.chalmers.se (Daniel Berglund) says: > I have a question about the "CAS-before-RAS" refresh mode found in certain > DRAMs (specifically, 4464 (64Kx4)). The data sheet states that the chip will > generate the row address internally. Does this mean that the only thing I will > have to do to keep the memory refreshed is to toggle CAS and RAS with the > prescribed timing every once in a while? Yup, as long as you get enough CAS-before-RAS cycles out within the prescribed refresh time, you're refreshing. Each DRAM has an internal counter than gets banged on each CAS-before-RAS refresh cycle. MUCH easier than building a row counter and all, if you're building the memory controller by hand (eg, TTL/PAL). This feature started showing up around the time 256K desity DRAMs came out (256kx1 and 64kx4), so it's in most of those, and far as I know all 1 meg and higher density parts. > Daniel Berglund (foperator@tekno.chalmers.se, BITNET: FOP@SECTHF51) > Chalmers University of Technology, G|teborg, Sweden -- Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Too much of everything is just enough
phil@diablo.amd.com (Phil Ngai) (11/11/89)
In article <3056@tekno.chalmers.se> foperator@tekno.chalmers.se (Daniel Berglund) writes: |Does this mean that the only thing I will |have to do to keep the memory refreshed is to toggle CAS and RAS with the |prescribed timing every once in a while? Yes, it works, I do it all the time. Clever people, those Japanese. -- Phil Ngai, phil@diablo.amd.com {uunet,decwrl,ucbvax}!amdcad!phil Come witness the failure of democracy in California!
mark@mips.COM (Mark G. Johnson) (11/11/89)
In article <28012@amdcad.AMD.COM> phil@diablo.AMD.COM (Phil Ngai) writes: > [re CAS before RAS refresh including builtin refresh address counter] > >Yes, it works, I do it all the time. Clever people, those Japanese. > No. Twere invented by the US arm of the British firm (at the time) Inmos. Thank a fellow named S. Sheffield Eaton. This is also where the ubiquitous "nibble mode" was invented. For DRAM ultra-trivia fanatics, which Japanese company bought the rights to produce the very fast 64K, 256K, and 1Mbit DRAMS that Eaton et al (Inmos) designed and prototyped? NMB Semiconductor. Their ads brag about speed speed speed. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 (408) 991-0208 mark@mips.com {or ...!decwrl!mips!mark}