vincel@fs0.ee.ubc.ca (vincent li) (01/11/90)
Hello folks. I am developing an expert advisor for my thesis and is confused on
the following piece of knowledge on (static) memory. On most memory data sheets
the *access time* of the data is usually given by two parameters:
tAA - address access time, time when address is valid to data is valid
tACS - chip select access time, time when chip select is asserted to when
data is valid.
These are for the read cycle. So, in calculations, do I use tACS or tAA?
The conclusion I've made is that the chip select usually controls the address
decoding units within the RAM and address decoding cannot begin until the
CS is asserted. The access time is the time when the address into the RAM
start getting decoded to when the valid data from the memory matrix appears
or can appear on the data bus. Thus, I believe you should use the tAA if
CS is asserted BEFORE the address is valid, and use tACS otherwise, but am
not sure.
Basically, if my definition of the access time is correct, then everything
should be straight forward, right?
Thanx for the help.
------------------------------------------------
vincel@ee.ubc.ca |-) If you study too much your brain will get so heavy
vinceli@triumfcl.bitnet %-| that it will begin to sag, lodge in the neck, and
|-( cut off breathing. -- Mr. Boffomikemc@mustang.ncr-fc.FtCollins.NCR.com (Mike McManus) (01/11/90)
In article <929@fs1.ee.ubc.ca> vincel@fs0.ee.ubc.ca (vincent li) writes: > The conclusion I've made is that the chip select usually controls the address > decoding units within the RAM and address decoding cannot begin until the > CS is asserted. Not necessarily so. It may happen that in some designs, the CS does not gate the address input (altho, *USUALLY* this is so), but instead may simply gate (or tristate) the outputs of the RAM/ROM. > The access time is the time when the address into the RAM > start getting decoded to when the valid data from the memory matrix appears > or can appear on the data bus. Thus, I believe you should use the tAA if > CS is asserted BEFORE the address is valid, and use tACS otherwise, but am > not sure. What you really need to do is to use the parameter that gives the worst-case read time. For example, if tAA is spec'ed at 20nS and tCS is 25nS, then even if CS is asserted 3nS before the address is valid, the read time is still defined by tCS = 25nS. One thing to keep in mind is that in most memory systems, the CS are made from high-order address bits. In other words, in a system which has 64K of memory (but who would want to work on such a system? :-), there would be 16 address lines to decode. Assume that the system uses 16K RAM chips. This would require 14 address lines to go to each chip, with 4 address lines left over to be decoded and used as chip selects. The time that it takes to decode the address lines to get the CS signals would obviously be critical. But, to simplify, assume that this decode could happen instantaneously (in fact, using some ROM/RAM chips that provide multiple CS's, a small system like this could be build without the extra CS decode circuitry). Then the *REAL* read access time is simply MAX( tAA, tCS). In the non-simplified case, it is MAX( tAA, tCS + CS decode overhead). Of course, not all architectures use this scheme, but it is common in simpler systems. Hope this helps! -- Disclaimer: All spelling and/or grammer in this document are guaranteed to be correct; any exseptions is the is wurk uv intter-net deemuns. Mike McManus (mikemc@ncr-fc.FtCollins.ncr.com) NCR Microelectronics 2001 Danfield Ct. mikemc@ncr-fc@ncr-sd.sandiego.ncr.com, or Ft. Collins, Colorado mikemc@ncr-fc@ccncsu.colostate.edu (303) 223-5100 Ext. 360 (they're ugly, but they work!)
davidc@vlsisj.VLSI.COM (David Chapman) (01/12/90)
In article <929@fs1.ee.ubc.ca> vincel@fs0.ee.ubc.ca (vincent li) writes: >Hello folks. I am developing an expert advisor for my thesis and is confused on >the following piece of knowledge on (static) memory. On most memory data sheets >the *access time* of the data is usually given by two parameters: >tAA - address access time, time when address is valid to data is valid >tACS - chip select access time, time when chip select is asserted to when >data is valid. Static RAM chips are supposed to be asynchronous devices. If CS is active, the outputs are supposed to be the data for whatever address is on the inputs. tACS is probably the time required to turn on the bus drivers and tAA is the time it takes to read data after an address changes. For fast SRAMs (i.e. all recent chips) these are often the same order of magnitude. For 250 ns SRAMs, for example, tCS should be much less than tAA. Note that this means that if the address lines change while CS is active, the data outputs will change a maximum of tAA later. Output data is NOT latched by CS going active! With respect to your modelling: data will be valid at the *later* of: (address lines stable + tAA) or (CS active + tACS). There is probably yet another time associated with the read signal going active. The same principle applies. -- David Chapman {known world}!decwrl!vlsisj!fndry!davidc vlsisj!fndry!davidc@decwrl.dec.com
hue@netcom.UUCP (Jonathan Hue) (01/12/90)
In article <929@fs1.ee.ubc.ca> vincel@fs0.ee.ubc.ca (vincent li) writes: >These are for the read cycle. So, in calculations, do I use tACS or tAA? >The conclusion I've made is that the chip select usually controls the address >decoding units within the RAM and address decoding cannot begin until the >CS is asserted. You should be able to tell from the block diagram on the data sheet if this is the case (it usually is). Most parts I've used use /CS for gating row and column address, and the input for writes. The access time is the time when the address into the RAM >start getting decoded to when the valid data from the memory matrix appears >or can appear on the data bus. Thus, I believe you should use the tAA if >CS is asserted BEFORE the address is valid, and use tACS otherwise, but am >not sure. For most parts I've used the two are spec'd at the same value. tAA (or tACC, as I've seen it, your tACS I've seen called tCO) is for when you're continuously holding /CS low. -Jonathan