johnw@watnext.waterloo.edu (John Wieczorek) (01/21/90)
According to the data sheets for the various members of the 68K family,
an intialization interval with reset and halt asserted of 100 milliseconds
is necessary to allow "stabilization of the on-chip circuitry and system
clock."
I find it hard to believe that a chip with an 8 MHZ clock requires
800000 cycles to stablize. Has this thing got some weird substrate
generator or what?
The reason for my examination of this rating is that I wish to incorporate
a 68008 into a battery power unit that spends most of its time sleeping,
but is awakened at 8 Hz. Such an interrupt driven system wouldn't be much
fun if I've got to give it .1 sec of warm-up to perform 100 usec of work,
(most of the time).
The 68008 was chosen because I need fast 32 bit integration. My sensor
(a photo diode monitoring a photoflash) is first logged, A to D'ed (at 8
bits in 5 us), read in, anti-logged (via lookup table) and summed. The
circuit has a 5 decade dynamic range with a 1 : 1.09 resolution. At this
point I'm considering using one of those weird intel 8096 series devices
because they have a power down mode and some speed but require my time and
effort in fiquiring them out and get the development software.
If any you, my hardware brethren, have insights or better yet a 68K board
made up that this might be tested on I'd gatefully and humbly be thankful
for your help.
Thanks in advance
John Wieczorek
johnw@watnext.waterloo.cachuck@mitlns.mit.edu (01/22/90)
-Message-Text-Follows- In article <13036@watcgl.waterloo.edu>, johnw@watnext.waterloo.edu (John Wieczorek) writes... > If any you, my hardware brethren, have insights or better yet a 68K board >made up that this might be tested on I'd gatefully and humbly be thankful >for your help. > > Thanks in advance > > John Wieczorek >johnw@watnext.waterloo.ca Using an external clock can solve the problem....