phupp@warwick.ac.uk (S Millington) (01/30/90)
I'm thinking about building a board for my A500, however some slightly
involved logic is required. Is there any intrinsic benfit from using PAL's
rather than separate logic chips - apart from the obvious board looking
nicer/reduced chip count. I have no facilities for programming pals and so do
not want to go to the trouble if they have no advantages - other than
mentioned above, which I can live with.
Thanks.
Stuart Millington.
phupp@poppy.yahoo@unix.cis.pitt.edu (Kenneth L Moore) (01/30/90)
In article <358@poppy.warwick.ac.uk> phupp@warwick.ac.uk (S Millington) writes:
=> I'm thinking about building a board for my A500, however some slightly
=>involved logic is required. Is there any intrinsic benfit from using PAL's
=>rather than separate logic chips - apart from the obvious board looking
=>nicer/reduced chip count. I have no facilities for programming pals and so do
=>not want to go to the trouble if they have no advantages - other than
=>mentioned above, which I can live with.
=>Stuart Millington.
The PAL should be faster as there is no chip to chip barrier. Would speed be
important in an "A500" board? Whatever that is.
--
I don't yell and I don't tell and I'm grateful as hell: Benny Hilllogajan@ns.network.com (John Logajan) (01/30/90)
In article <358@poppy.warwick.ac.uk> phupp@warwick.ac.uk (S Millington) writes: >Is there any intrinsic benfit from using PAL's >rather than separate logic chips I have to make that type of decision all the time. In a production environment, PALS are expensive to program and install (they require sockets) and you need a bureaucracy to keep track of the "firmware" level. The forces on me, then, are to avoid using PALS. One nice feature, however, is that if I screw up (really! It has been known to happen even to me!) it is often easy to burn a new PAL with a few changes, and the boss doesn't even have to know anything went wrong. For home use, if I had a PAL Burner, I would probably use PALS whenever I could to reduce layout/wire-wrap work. Since I don't have a home PAL-burner I tend to use standard logic (but since I don't really do much home stuff anymore, I guess I can't really say I use ANYTHING.) -- - John Logajan @ Network Systems; 7600 Boone Ave; Brooklyn Park, MN 55428 - logajan@ns.network.com, john@logajan.mn.org, 612-424-4888, Fax 424-2853
chuck@mitlns.mit.edu (01/30/90)
-Message-Text-Follows- In article <358@poppy.warwick.ac.uk>, phupp@warwick.ac.uk (S Millington) writes... > I too am a budding pal user. Most of my designs require low cost and low power. I note that the standard PALs are available from JDR for $2.50-$5.00, which is in my range. But these chew up 30-50ma. Are there any fully static cmos chips available? I.e. << 1ma when not switching? Any that are cheap and readily available? Particularly nice would be one that could handle demultiplexing a bus and decoding simultaneously (standard 8 bit data/address). This would require a lot of pins, say 12 input and 12 output, but hey, why not ask for the moon? Chuck Parsons CHUCK@MITLNS.MIT.EDU
nogeea@hw-4h625.UUCP (Allen Nogee) (01/30/90)
In article <358@poppy.warwick.ac.uk>, phupp@warwick.ac.uk (S Millington) writes: > > I'm thinking about building a board for my A500, however some slightly > involved logic is required. Is there any intrinsic benfit from using PAL's > rather than separate logic chips - apart from the obvious board looking > nicer/reduced chip count. I have no facilities for programming pals and so do > not want to go to the trouble if they have no advantages - other than > mentioned above, which I can live with. You might want to also consider EPLDs. (Eraseable Programmable Logic Devices) With ALTERA being a major vendor. I use these many times in my designs at work. These are much more powerful than PALs but also more expensive. They can be erased and reprogrammed. Several companies sell IBM PC card type programmers. It might cost more at first to get started with EPLDs, they have much more uses in the long run.
markz@ssc.UUCP (Mark Zenier) (01/31/90)
In article <1990Jan29.225838.2711@athena.mit.edu>, chuck@mitlns.mit.edu writes: > I too am a budding pal user. Most of my designs require low cost and > low power. I note that the standard PALs are available from JDR for > $2.50-$5.00, which is in my range. But these chew up 30-50ma. Are there Some of the old/fast ones take up to 180 mA. gack. > any fully static cmos chips available? I.e. << 1ma when not switching? > Any that are cheap and readily available? Three different lines. GALs from Lattice. (And National ?) PEELS from ICT, and Gould. EP-3x0's from Altera and Intel A couple of references. Programmable Logic Designer's Guide by Roger C. Alford. 1989 Howard W. Sams & Co. "Create Your Own IC's", Bill Green, January 1990 Popular Electronics A kit project for a PEEL programmer. A z80 based one board project. But he used a PEEL in the design, in addition to the eprom, so you have to buy his kit. @#$%^&! Oh well, it's cheap ($80) even if it only accepts keyboard input. markz@ssc.uucp
dalyb@godzilla.UUCP (Brian Daly) (01/31/90)
In article <1990Jan29.225838.2711@athena.mit.edu>, chuck@mitlns.mit.edu writes: > I too am a budding pal user. Most of my designs require low cost and > low power. I note that the standard PALs are available from JDR for > $2.50-$5.00, which is in my range. But these chew up 30-50ma. Are there > any fully static cmos chips available? I.e. << 1ma when not switching? > Any that are cheap and readily available? You might want to check out the Signetics PLD Data manual. I believe they may have what you are looking for. I don't have any information as to availability or price, however. Brian Daly WB7OML -- Brian K. Daly WB7OML @ AG Communication Systems, Phoenix, Arizona UUCP: {...!ames!ncar!noao!asuvax | uunet!zardoz!hrc | att}!gtephx!dalyb Phone: (602) 582-7644 FAX: (602) 582-7111 ~
elliott@optilink.UUCP (Paul Elliott x225) (01/31/90)
The original PALs (by MMI?) were bipolar devices, the ever-popular
16R8 and 16L8 being typical devices. These had a raw speed of perhaps
15ns tpd in-to-unregistered-out (typical speeds given), and consumed
about 140 mA @ 5V. These were quickly followed by "half-power" devices
(25 ns, 75 mA). Both of these families remain very popular, with the low-
power parts being most popular; the speeds being in the LSTTL ballpark.
The advantage of these PALS over random logic is board area, flexability,
and a "flattening" effect on the logic, yielding faster performance than
the typical TTL equivalent. The disadvantages are generally higher cost
and increased power consumption. The 16L8 has 10 inputs, one output, and
7 selectable inputs-or-outputs. There are higher density bipolar PALS as well.
CMOS PALs were first introduced by Harris (I think) and were "zero standby
power" types, but were significantly slower than the bipolar PALS. Altera
(second-sourced by Intel) introduced the EP300 PAL which was moderate power,
good speed, and had a very flexable "output macrocell" structure. Altera, and
other manufacturers have followed up with larger, faster, lower-power devices.
Ballpark data:
Part No. Vendor Tpd max ICC (max idle) Price (moderate qty)
16L8 everyone 25ns 180mA $1.00 ?
16L8 lowpwr everyone 35ns 90mA $1.00 ?
16CL8 cmos TI 55ns 100uA ?
EP310 cmos Altera 35ns 30mA $5.00 ?
EP320 cmos Altera 25ns 150uA $7.00 ?
These are all 20-pin PALS. The Altera parts are available with a windowed lid
so they can be erased with an EPROM eraser if you goof (or if marketing
changes their minds). The bipolar PALS are one-shot devices. Unlike EPROM
vendors, the cmos PAL suppliers are _very_ reluctant to release the programming
specs, so it is difficult to roll your own programmer. I've not even touched
on the many more specialized state-machine type PALS or the larger devices.
All prices are guestimates, your mileage may vary. Other vendors include
National Semiconductor, AMD, and many others.
--
Paul M. Elliott Optilink Corporation (707) 795-9444
{pyramid,pixar,tekbspa}!optilink!elliott
"The dog ate my disclaimer."phupp@warwick.ac.uk (S Millington) (01/31/90)
In article <21960@unix.cis.pitt.edu> yahoo@unix.cis.pitt.edu (Kenneth L Moore) writes: >In article <358@poppy.warwick.ac.uk> phupp@warwick.ac.uk (S Millington) writes: [deleted] >=>Stuart Millington. > >The PAL should be faster as there is no chip to chip barrier. Would speed be >important in an "A500" board? Whatever that is. > >-- >I don't yell and I don't tell and I'm grateful as hell: Benny Hill The A500 is a Comodore Amiga A500. As for speed the logic is being used to control multi-board 68000 bus request-grant-acknowleges ( up to 5 boards) and to prevent multiple boards responding to the same event. I'll have to have a close look at the timing and see if I can get away with fast 74 series chips. Thanks to all. Stuart Millington. phupp@poppy.
ma62141@etana.tut.fi (Antila Marko) (01/31/90)
From article <442@ssc.UUCP>, by markz@ssc.UUCP (Mark Zenier): > In article <1990Jan29.225838.2711@athena.mit.edu>, chuck@mitlns.mit.edu writes: >> I too am a budding pal user. Most of my designs require low cost and >> low power. I note that the standard PALs are available from JDR for >> $2.50-$5.00, which is in my range. But these chew up 30-50ma. Are there > Some of the old/fast ones take up to 180 mA. gack. >> any fully static cmos chips available? I.e. << 1ma when not switching? >> Any that are cheap and readily available? > Three different lines. > GALs from Lattice. (And National ?) > PEELS from ICT, and Gould. > EP-3x0's from Altera and Intel A PEEL18CV8 (Programmable, Electrically-Erasable Logic) chip from ICT consumes 20mA + 0.7mA/MHz and maximum typical delay is 35ns. It costs about 8FIM (less than 2US$) apiece, less in quantities. When we ordered 50 pcs of these chips we got also some pc software for programming these devices. The PEEL18CV8 - chip consists of 10 inputs and 8 outputs/inputs. One of the inputs can also be configured as master clock input. Internally it has synchronous set and asynchronous reset, and 8 macrocells. This data is from ICT's "PEEL Software and Applications Handbook." I'm just happy (and heavy) PEEL-user, no other associations with ICT. > ... some references deleted ... > markz@ssc.uucp * Marko Antila (ma62141@tut.fi) ! Studying Wonders of * * Tampere University of Technology ! Electronics @ TTKK * * Signal Processing Lab, P.O.Box 527 ! ====================== * * SF-33101 Tampere, Finland ! Vacuum tube rules OK *
phil@pepsi.amd.com (Phil Ngai) (02/01/90)
Let's not forget 15 ns, half-power, electrically-erasable PALs, in
the 16V8 flavor and the 20V8 flavor. Priced to compete with bipolar PALs
of the same speed, they seem almost too good to be true. I think there
are also quarter power EE PALs available now.
Wouldn't you rather fix your mistakes with a text editor than with a
wire-wrap gun?
--
Phil Ngai, phil@diablo.amd.com {uunet,decwrl,ucbvax}!amdcad!phil
Peace through strength.phil@ingr.com (Phil Johnson) (02/01/90)
In article <358@poppy.warwick.ac.uk> phupp@warwick.ac.uk (S Millington) writes: > > I'm thinking about building a board for my A500, however some slightly >involved logic is required. Is there any intrinsic benfit from using PAL's >rather than separate logic chips - apart from the obvious board looking >nicer/reduced chip count. I have no facilities for programming pals and so do >not want to go to the trouble if they have no advantages - other than >mentioned above, which I can live with. The use of programmable logic devices (PAL, IFL, etc) can reduce the total chip count of a design, therefore reduce the cost in most cases. The cost savings is part of the design cycle, so you will need to cost the discrete versus the PLD design. The reduction factor will vary according to the circuit, but you can normally get 3 to 12 chips (7400-type) into a single PLD. Also, by reducing the chip count you can normally expect a more reliable circuit. An example would be an address decoder circuit using 4 to 6 discrete chips versus a single PLD. (QUALIFIER: Reliability is directly proportional to the care taken in the circuit design and selecting the parts.) Most local manufacturers office or distributors have the programming facilities and allow you to bring in either a fuse equation table or fuse file, buy the PLD from them and then program the device. I recommend that you look at several different types of PLDs. I use PALs, but have found the the Signetic IFLs produce a higher reduction factor for a number of designs. -- Philip E. Johnson UUCP: usenet!ingr!b3!sys_7a!phil MY words, VOICE: (205) 772-2497 MY opinion!
mmm@cup.portal.com (Mark Robert Thorson) (02/02/90)
For a person without a programmer, the Logic Cell Array (LCA) family from Xilinx comes to mind. They're more like little gate arrays than they are like PAL's. Their configuration bits are static RAM cells programmed using any of a number of modes (selected by holding pins high or low). You can hook the LCA up to an EPROM, and let it read the bits in. You can clock the bits in like a shift register. You can strobe the bits in in parallel, like a FIFO. You can even set up one LCA to read in its configuration in parallel from a ROM, then daisy chain all the rest of the LCA's in the system like a big shift register. Another possibility is the ispGAL16Z8 (and that's the short form of the name, which doesn't specify speed or package type!) which can receive its programming serially, like a shift register. It's made by Lattice (or will be made by Lattice). It uses EEPROM bits, so the serial interface is only needed for reprogramming. (isp stands for in-system programmable.) It's an architectural superset of the 16Z8, but has four more pins. I'll bet there's some simple way to program this thing from a regular serial port, if you just dig out the baud rate clock. Possible second source for these chips is AMD, who has sued all the PLD companies, and gotten cross-licensing agreements with several of them.
henry@utzoo.uucp (Henry Spencer) (02/04/90)
In article <26516@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) writes: >For a person without a programmer, the Logic Cell Array (LCA) family from >Xilinx comes to mind. They're more like little gate arrays than they are >like PAL's. Their configuration bits are static RAM cells programmed using >any of a number of modes [external EPROMS, downloading, daisy-chaining] Unfortunately, a person without a programmer is totally up the creek in dealing with one of these beasts, because Xilinx will not tell you the mapping between circuit connections and programming bits. You have to buy their programming software, which isn't cheap. -- 1972: Saturn V #15 flight-ready| Henry Spencer at U of Toronto Zoology 1990: birds nesting in engines | uunet!attcan!utzoo!henry henry@zoo.toronto.edu
aez@Data-IO.COM (Adam Zilinskas) (02/06/90)
>> I'm thinking about building a board for my A500, however some slightly >>involved logic is required. Is there any intrinsic benfit from using PAL's >>rather than separate logic chips - apart from the obvious board looking >>nicer/reduced chip count. I have no facilities for programming pals and so do >>not want to go to the trouble if they have no advantages - other than >>mentioned above, which I can live with. > (please note that I come from a biased position, I make software for programming PALs, PICs, FPGAs and whatever alphabet soup chip that needs logic synthesis). Reasons for using PALs: 1. Inventory. Many of the larger PIC (Programmable IC) chips can emulate any TTL functions that you could use in a design. Its your choice to keep several 22V10's around or have 3-4 7400, 2-3 74163, 2-3 74151 ... 2. Board changes (only matters when making PCB, only slightly matters if doing wirewrap). A new PIC and be programmed and patch a circuit within hours/minutes compared to cutting traces on boards and patch wiring around. (this really depends upon how big is the screwup, changing a logic function is easy, getting a signal to a chip that was not there befor still needs a patch wire, but maybe no new chips). 3. Speed. Unless you have TTL functions that exactly meet your needs, you have to build composite circuits, having signals pass through multiple levels of logic and going between chips slows things down. Most PIC chips do their functions with 2-level logic (typically ORs of ANDs with some inverters, there are exceptions) and the going rate on the fastest PIC and like 2-7 nsec for a function, you win even more if the signal uses internal feedback and doesn't have to go through those slower pin buffers. 4. Density. 14->18 pin chips are fine, but when a design takes 10 small chips or 2-3 20 pin PICs, the PICs are cheaper in board real-estate. Reasons for not using PALs: 1. You have to program them. For productions lines of making thousands of anything, you want stuff in bulk. Each PIC has to be individually programmed and inserted into their right spot. Many companies [like mine :-) ] provide gang programmers to make this easier, the programming step essentially replaces the problem of getting the right TTL part out of inventory. 2. You have to program them. Most of the programming languages for PICs are more like computer programs and some hardware designers don't know how to program. Its one thing to understand a 7400 2 input NAND and another to figure out how to use the macrocell in a 22V10 to implement one bit of a shift register. (I am not ragging down on all hardware engineers, its just that the difference between PICs and "glue logic" (74xx parts) is akin to the difference between vacuum tubes and transistors, some engineers make the transistion, some do not, engineering darwinism :-) 3. You have to program them. A hobbyist can go to Radio Crack and get glue logic. Getting a PIC, getting the software to program it, then getting the box to program the chip is not at RS (at least not now :-). You can go to some distributers like Hamilton Avnet and if you talk to them nicely, they may let you use their equipment. For a hobbyist (I define that as anybody who is not making a living off their design, or can't afford the $$ for the equpiment so they still can't make a living off their design), I suggest that you become good friends with somebody who has a PIC programmer, you may be able to get to use his software and hardware. 4. Seat of the pants debugging falls by the wayside. When your circuit is packed into a 20 pin chip (18 points to put a scope probe on), just slapping together a design and changing it until it works becomes near impossible. You have to DESIGN (nasty thought %-), most PIC programs provide some sort of simulator that helps but in general, you have to do the right thing for the right thing to happen! I have tried to keep out any overt advertisements about what Data I/O provides compared to our competitors. If you ask, I can give you our toll free number and you may be able to ask for literature (and maybe demos) for both the hardware and software we provide. For our competitors, look them up in the various engineering magazines. Adam Zilinskas Data I/O corp Logic Synthesis Where blowing a fuse is sometimes a good thing.
toddpw@tybalt.caltech.edu (Todd P. Whitesel) (02/10/90)
elliott@optilink.UUCP (Paul Elliott x225) writes: >If anyone out there knows of an EP310-equivalent functionality part in a SMT >package, let me know. Even a low-power CMOS 16L8/16R8 would be nice. I know this is obvious, but haven't you asked your supplier? Almost everything from TI with 40 pins or less is available in DIP and SMT, because TI is committed to both package types and the advantages of each. I don't work for TI, but they have sent me lots of free data books. Todd Whitesel toddpw @ tybalt.caltech.edu
elliott@optilink.UUCP (Paul Elliott x225) (02/13/90)
In article <1990Feb9.214647.22868@spectre.ccsf.caltech.edu>, toddpw@tybalt.caltech.edu (Todd P. Whitesel) writes: > elliott@optilink.UUCP (Paul Elliott x225) writes: > >If anyone out there knows of an EP310-equivalent functionality part in a SMT > >package, let me know. Even a low-power CMOS 16L8/16R8 would be nice. > I know this is obvious, but haven't you asked your supplier? > Almost everything from TI with 40 pins or less is available in DIP and SMT, > because TI is committed to both package types and the advantages of each. Admittedly, I do occasionally overlook the obvious, but in this case, I _did_ call TI about the CMOS 16R8 in SMT. I had to wait two days for someone to call me back, then had to give the person on the other end of the phone line a brief education on how CMOS PALs were different from bipolar and ECL PALs (and were different from PROMs, etc). I could have given the problem to our purchasing or component engineering staff, but the problem resolved itself when I decided to pull the function in question inside the gate array I was doing. So, I remain ignorant on the availability of _small_ SMT CMOS PALs, and, lacking an immediate requirement for them don't plan to try very hard to rectify that. (Asking on the net is doesn't qualify as "very hard" :-) -- Paul M. Elliott Optilink Corporation (707) 795-9444 {pyramid,pixar,tekbspa}!optilink!elliott "The dog ate my disclaimer."
johnd@sco.COM (John DuBois) (02/13/90)
I asked this one a long time ago and didn't get answers...
What is a good reference/tutorial on designing with various programmable
logic devices?
John DuBois
johnd@sco.com