louis@asterix.drev.dnd.ca (Louis Demers) (03/19/90)
Hi,
This is the solution I use. It requires a clock and two parts ( 4 Xor
ie. LS86, 4 D FF ie. LS175 or LS174). It doesn't accumulate errors
when reversing direction. It is totally synchronous. It generates 4
counts per encoder cycle. The CounEnable is active high and therefore
might require inversion before being connected to most counters. If
like me, you implement this circuit along with its counter in a
PAL, this is not a problem.
The clock inputs (including the counters) must be reasonably higher
than the maximum frequency of either channel.
+-----------------\\-----\
------ A | ------ Az ||XOR1 >-----\\-----\
Lead --|D Q|---+---|D Q|--------//-----/ ||XOR3 >--Count Enable
| L1 | | | L2 | +--//-----/
> !Q| | > !Q| |
------ | ------ |
+-----------------\\-----\ |
||XOR4 >--|-------------up
+--//-----/ |
------ B ------ Bz | |
Lag --|D Q|---+---|D Q|-----+ |
| L3 | | | L4 | | |
> !Q| | > !Q| +--\\-----\ |
------ | ------ ||XOR2 >--+
+-----------------//-----/
L1, L2 and XOR1 form the transition detector for channel Lead
L3, L4 and XOR2 form the transition detector for channel Lag
XOR3 is used to combine both transition detectors. Since there
should not be a transition on both channels at the same time,
an "or" would do equally well.
XOR4 is used to determine the direction of the count I deduced it
using the following Karnaugh map (+ CW, - CCW, X don't care).
/---A---\
+---+---+---+---+
| X | - | X | + |
+---+---+---+---+-\
| - | X | + | X | |
/--+---+---+---+---+ B
| | X | + | X | - | |
Bz +---+---+---+---+-/
| | + | X | - | X |
\--+---+---+---+---+
\---Az--/
up(+) = (A !Bz) + ( !A Bz) = A xor Bz
--
| Louis Demers | DREV, Defence Research Establishment,Valcartier |
| louis@asterix.drev.dnd.ca | POBox 8800, Courcelette,Quebec, CANADA, G0A 1R0 |
| (131.132.48.2) | Office: (418) 844-4424 fax (418) 844-4511 |
+---------------------------+-------------------------------------------------+