john@frog.UUCP (John Woods) (04/10/90)
In the Motorola "CMOS/NMOS Special Functions Data Book", the section on
the MC145145-1 PLL synthesizer chip has a very interesting example use,
sketched below. Basically, it is a two loop synthesizer with 100Hz
output resolution, achieved not through the usual approach of having one
1Kc synth loop divided by 10, but rather by using one 10.1Mc crystal and
having one loop run with 10kc steps and the other loop has 10.1kc steps;
a microprocessor is used to figure out the right division rations to program
into the two chips.
7.9996 to 32.0184 MHz
10.1Mc 100 Hz Steps
| | ^
------------------------- |
| Xin Xout | ------------- ---------
| PD out |---->|LOOP FILTER|--->| VCO 1 |
| | ------------- _________
| | V
| PLL 1 | ---------
| Fin1 |<---------------------| mixer |
| | 3.9996 to 4.9995Mc ---------
| REFout | or 16.0085-17.0084Mc ^
------------------------- 10.100 kc steps |
| |
V |
------------------------- |
| Xin Xout | ------------- --------- 4.000 to
| PD out |---->|LOOP FILTER|--->| VCO 2 | 15.0100
| | ------------- _________ MHz
| PLL 2 | | 10KHz steps
| | |
| Fin2 |<--------------------------
| |
| |
-------------------------
(programming, chip select, etc. left out) PLL 1 divides the 10.1Mc reference
by 1000 to get an internal reference of 10.1Kc, and PLL 2 divides the reference
by 1010 to get an internal reference of 10.0Kc (three cheers for fully
programmable reference dividers).
The programming information shows how to tune from 7.9996 to 32.0184 MHz
by varying Fin1 and Fin2. The Fin1 range of 3.9996 to 4.9995 is used
for the Fvco1 range of 7.9996 to 20.0095.
The question I have is this: Assume we want to generate 20.0000 MHz. We
program 1596 into PLL 2 (so VCO2 is at 15.9600Mc) and 404 into PLL 1 (so
Fin1 is at 4.0400Mc). This would imply VCO1 is at 20.000, just as desired.
BUT: why can't VCO1 lock in at 11.9200Mc, the difference of VCO2 and
Fin1? The application diagram doesn't give any hints. Is the answer that
one circuit cannot really cover the entire range from 7.9996 to 32.0184Mc
(thus putting the VCO1 "image" frequency outside its range of adaptability)
or is there some other trick I am missing?
A more general question: I have seen other fine-resolution PLL synthesizers
that run one PLL at a very high frequency (like 200MHz) and divide by 100
to mix with the other loop, so that each loop runs with (say) 1Kc granularity.
It seems to me that this dual-granularity trick can be done with simpler
electronics; is there any technical reason for preferring one over the
other? Perhaps I am overestimating the difficulty of building a 200MHz
VCO that runs cleanly (my construction abilities appear to leave something
to be desired...).
--
John Woods, Charles River Data Systems, Framingham MA, (508) 626-1101
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