[sci.electronics] Metal Migration

straka@cbnewsc.att.com (richard.j.straka) (05/24/90)

In article <15572@vlsisj.VLSI.COM> davidc@vlsisj.UUCP (David Chapman) writes:
>In article <322@garth.UUCP> obnoid@garth.UUCP (Michael Kirschner) writes:
>>In article <21000076@m.cs.uiuc.edu> kenny@m.cs.uiuc.edu writes:
>>>
>>>You *can* exceed the `absolute maximum ratings' of CMOS devices if you
>>>take care to limit current; the protection diodes will generally handle
>>>about 10 mA without any problems.
>
>Metal migration is bad enough, but the problem is that it's driven by
>current density.  So if you get necking at some point, the current
>
>An amusing story (I won't name names because it will embarrass a rather
>well-known company):  on our old HMOS process, we spec'd a current density

Another amusing story.  I saw it.  With my OWN eyes.  It is TRUE.  NO joke.

Back in the old days of EPROMS (4Kbit P-channel), the product engineer of
this animal (company shall remain unnamed, although it shouldn't be very
hard to pinpoint with the above information) showed me this cute phenomenon:

At wafer probe, the 50V or so of programming voltage was too much for the
chip to handle, so they were "pushed-out" with pulses of 20V, 25V, ...
for a while, causing a LOT of localized heating, thus actually changing the
profile of the metallurgical junction, enabling it to handle the increased
voltage without breaking down.  Yes, this is bizarre stuff, but read on; it
gets better:

He said: "Hey, take a look at this!"  We went over to a wafer probe station,
and during the first probing of the raw wafer, the above mentioned "push-out"
got a metal line so hot that when viewing it under the probe microscope (with
a probe cloth to block out light), you could actually see the metal line
faintly, but distinctly INCANDESCE!  Can you say flakey process?  Yes, real
production-line stuff.  Thank God for N-channel EPROMs which are a LOT easier
to program (physics helps out a LOT).
-- 
Richard Straka                  AT&T Bell Laboratories, IH-6K311
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