adamd@rhi.hi.is (Adam David) (11/18/90)
I am interested in how RAM access times are specified. Say a 150ns RAM chip is read and immediately written again without changing the address or deselecting the chip between. What is the total time taken? The read cycle must take 150ns, but when the write cycle begins the correct memory cell is already addressed. How long does it take to actually write to (or read from) a memory cell without considering addressing delays? Does anyone have experience or other inside knowledge about this issue? Would there be any difference between the times for SRAM or DRAM? Thanks ahead for any help, Adam David. adamd@rhi.hi.is
henry@zoo.toronto.edu (Henry Spencer) (11/19/90)
In article <2416@krafla.rhi.hi.is> adamd@rhi.hi.is (Adam David) writes: >I am interested in how RAM access times are specified. Say a 150ns RAM chip is >read and immediately written again without changing the address or deselecting >the chip between. What is the total time taken? The read cycle must take 150ns, >but when the write cycle begins the correct memory cell is already addressed. >How long does it take to actually write to (or read from) a memory cell without >considering addressing delays? It depends on the chip, is the fast answer. Assuming you are talking about reading and then writing the *same* location -- you don't make that clear -- then there can sometimes be a speed improvement. A lot depends on the details of the memory technology you are using. You're also overlooking another complication: the speed quoted for a chip is usually the read access time. That is *not* necessarily the full time needed for a read cycle. DRAMs, in particular, need recovery time after the read, and thus have a cycle time substantially longer than their access time. On the other hand, they can also do read-modify-write cycles that take less time than independent reads and writes. A DRAM data sheet will often spend five pages on functional description and electrical parameters, followed by ten pages of timing diagrams and tables of timing limits. A precise answer would require a far more detailed question. -- "I don't *want* to be normal!" | Henry Spencer at U of Toronto Zoology "Not to worry." | henry@zoo.toronto.edu utzoo!henry
ftpam1@acad3.fai.alaska.edu (MUNTS PHILLIP A) (11/19/90)
In article <2416@krafla.rhi.hi.is>, adamd@rhi.hi.is (Adam David) writes... >I am interested in how RAM access times are specified. Say a 150ns RAM chip is >read and immediately written again without changing the address or deselecting >the chip between. What is the total time taken? The read cycle must take 150ns, >but when the write cycle begins the correct memory cell is already addressed. >How long does it take to actually write to (or read from) a memory cell without >considering addressing delays? > >Does anyone have experience or other inside knowledge about this issue? >Would there be any difference between the times for SRAM or DRAM? > >Thanks ahead for any help, > >Adam David. adamd@rhi.hi.is Read access times for static RAM is generally specified from chip select going active OR address lines going stable, whichever happens last. The minimum read cycle time is the same as the access time, but can only occur if chip select is continuously active and the address lines change instantaneously exactly every access time. This is of course impossible in the real world. (With fast, registered address buffers you could get pretty doggone close.) If you never change the address and hold chip select active, you can perform infinitely fast read cycles, of course. :-) Write cycles are a bit more complex and vary somewhat among manufacturers. Some allow shorter write cycles but the NEC Memory Products Data Book I happen to have at hand specifies write cycles at the same duration as read cycles. If you add up all the individual pieces of the cycle, however, the minimum total is quite a bit less than the total cycle time specified. So you might be able to get away with faster write cycles but this would be bad engineering practice for anything intended to be marketed. Cycle times for dynamic RAM are almost always longer than the access times because of the address multiplexing overhead and something called the precharge time. DRAM is beyond the scope of my experience and I can't say much more. Philip Munts NRA Extremist, etc. University of Alaska, Fairbanks
adamd@rhi.hi.is (Adam David) (11/20/90)
In <1990Nov18.225425.22234@zoo.toronto.edu> henry@zoo.toronto.edu (Henry Spencer) writes: >In article <2416@krafla.rhi.hi.is> adamd@rhi.hi.is (Adam David) writes: >>I am interested in how RAM access times are specified. Say a 150ns RAM chip is >>read and immediately written again without changing the address or deselecting >>the chip between. What is the total time taken? The read cycle must take 150ns, >>but when the write cycle begins the correct memory cell is already addressed. >>How long does it take to actually write to (or read from) a memory cell without >>considering addressing delays? >It depends on the chip, is the fast answer. Assuming you are talking about >reading and then writing the *same* location -- you don't make that clear -- >then there can sometimes be a speed improvement. A lot depends on the >details of the memory technology you are using. Yes, I definitely meant reading the memory contents before writing new data at the same location. I was interested in the comparison between various types of memory but am specifically interested in the newer pseudo-static DRAMs (with on-chip refresh circuitry for times of little activity). I have no access to the data sheets for any of these at present. >You're also overlooking another complication: the speed quoted for a chip >is usually the read access time. That is *not* necessarily the full time >needed for a read cycle. DRAMs, in particular, need recovery time after >the read, and thus have a cycle time substantially longer than their access >time. On the other hand, they can also do read-modify-write cycles that >take less time than independent reads and writes. A DRAM data sheet will >often spend five pages on functional description and electrical parameters, >followed by ten pages of timing diagrams and tables of timing limits. A >precise answer would require a far more detailed question. Let me guess... , pseudo-static DRAMs are still DRAMs although they have an 8-bit data path and non-multiplexed address lines. Therefore they have similar characteristics internally and would take a while longer to complete a full access cycle at any particular address than the quoted access times. With 150ns RAM a single read cycle followed by a single write cycle would take 150ns plus some recovery time, twice over. A combined read-write cycle would take twice 150ns plus the recovery time once. If this is true the write part of the cycle may not begin until the first 150ns are over, to allow the data to be read. Is this in fact the case? Does this then mean that no greater speed is possible for data exchange operations without moving to faster components? For completeness, here is the order of signals (still guessing): ._______________________________________________. Address lines. ___| stable address of valid memory location |_____ |_______________________________________________| _______________. ._________ /CE. |_______________________________________| _________________. ._______________________________ /OE. |_______________| ___________________________________. ._____________ /WE. |_______________| .__.._________________. Data lines. __________________________|rd||stable write data|___________ |__||_________________| each horizontal bar represents 10 ns. Is this the best performance we can expect from the memory chip? Or must it be even worse for any/all single-ported devices? Thanks for any replies. Adam David. adamd@rhi.hi.is
ftpam1@acad3.fai.alaska.edu (MUNTS PHILLIP A) (11/21/90)
In article <2425@krafla.rhi.hi.is>, adamd@rhi.hi.is (Adam David) writes... >Yes, I definitely meant reading the memory contents before writing new data at >the same location. I was interested in the comparison between various types of >memory but am specifically interested in the newer pseudo-static DRAMs (with >on-chip refresh circuitry for times of little activity). I have no access to the >data sheets for any of these at present. > >Let me guess... , pseudo-static DRAMs are still DRAMs although they have an >8-bit data path and non-multiplexed address lines. Therefore they have similar >characteristics internally and would take a while longer to complete a full >access cycle at any particular address than the quoted access times. With 150ns >RAM a single read cycle followed by a single write cycle would take 150ns plus >some recovery time, twice over. A combined read-write cycle would take twice >150ns plus the recovery time once. If this is true the write part of the cycle >may not begin until the first 150ns are over, to allow the data to be read. >Is this in fact the case? Does this then mean that no greater speed is possible >for data exchange operations without moving to faster components? > >For completeness, here is the order of signals (still guessing): > > ._______________________________________________. >Address lines. ___| stable address of valid memory location |_____ > |_______________________________________________| > > _______________. ._________ >/CE. |_______________________________________| > > _________________. ._______________________________ >/OE. |_______________| > > ___________________________________. ._____________ >/WE. |_______________| > > .__.._________________. >Data lines. __________________________|rd||stable write data|___________ > |__||_________________| > > >each horizontal bar represents 10 ns. > >Is this the best performance we can expect from the memory chip? >Or must it be even worse for any/all single-ported devices? > >Thanks for any replies. > >Adam David. adamd@rhi.hi.is Just happen to have a new data sheet from Motorola, for the MCM518128, a 128K x 8 PSRAM. Parameters for 80 and 100 ns parts are listed, but I will consider here only the 100 ns device. The random read or write cycle time is 160 ns minimum. The chip select access time is 100 ns. The precharge time (chip select inactive) is 50 ns. I presume the missing 10 ns is lost in transition times. The read-modify-write, which follows your diagram nicely (good guessing!) has a minimum cycle time of 235 ns. Note that the output drivers require as much as 30 ns to turn off. (In other words, wait 30 ns after deactivating the read pulse before driving write data onto the bus.) I have data sheets for one or two other PSRAM's but I suspect they are pretty much the same. I was originally interested in them because the address is latched on the falling edge of chip select, allowing the address latches to be eliminated on a multiplexed address/data bus. Philip Munts N7AHL NRA Extremist, etc. University of Alaska, Fairbanks
Mike.McManus@FtCollins.NCR.com (Mike McManus) (11/26/90)
In article <2425@krafla.rhi.hi.is> adamd@rhi.hi.is (Adam David) writes: > >>I am interested in how RAM access times are specified. Say a 150ns RAM > >>chip is read and immediately written again without changing the address > >>or deselecting the chip between. What is the total time taken? The read > >>cycle must take 150ns, but when the write cycle begins the correct memory > >>cell is already addressed. How long does it take to actually write to > >>(or read from) a memory cell without considering addressing delays? > > Yes, I definitely meant reading the memory contents before writing new data > at the same location. I was interested in the comparison between various > types of memory but am specifically interested in the newer pseudo-static > DRAMs (with on-chip refresh circuitry for times of little activity). I have > no access to the data sheets for any of these at present. > > >You're also overlooking another complication: the speed quoted for a chip > >is usually the read access time. That is *not* necessarily the full time > >needed for a read cycle. DRAMs, in particular, need recovery time after > >the read, and thus have a cycle time substantially longer than their access > >time. On the other hand, they can also do read-modify-write cycles that > >take less time than independent reads and writes. ... > With 150ns RAM a single read cycle > followed by a single write cycle would take 150ns plus some recovery > time, twice over. A combined read-write cycle would take twice 150ns plus > the recovery time once. If this is true the write part of the cycle may > not begin until the first 150ns are over, to allow the data to be read. > Is this in fact the case? Does this then mean that no greater speed is > possible for data exchange operations without moving to faster components? As a disclaimer, I'm not very familiar with DRAMS, but am familiar with psuedo-static RAMs. That said... A true PS RAM requires a clock to cycle between a "precharge" and an "access" phase. During precharge, all internal bitlines (the actuall connections to the output of the RAM cells) are charged to a static state, usually HIGH. The requires Tpre amount of time. During a read, the accessed call must then pull a charged bitline low to read a 0 state, but simply leaves the bitline in a charged state to read a 1 (or vice versa) rather then pulling it high. This takes Tacc time. The total cycle time, Tcyc = Tpre + Tacc. For a write, things are not (necessarily) the same. The way we spec our write time for PS RAMs is the amount of time that it takes to move a bitline to it's opposite state, and write the cell connected to that bitline. So the time to write a 1 is the time it takes to over-write a cell containing a 0, and vice versa to write a 0. The Twrite is the maximum of these two. Notice that the write does *NOT* take into account Tpre, nor is it required that a precharge occur before a write, because of the way we spec it (also note, however, that I do not know what convention is used by others). For simplicity sake, though, Tcyc is still spec'd as Tpre + Tacc, given that Twrite < Tacc, and the part is clocked. We have also started to spec a Trmw (read-modify-write time, what you asked about), which we define as Tpre + Tacc + Twrite, which is roughly 1.5*Tacc. Some SRAMs (static RAMs), and I assume some DRAMs as well, may be PS internally, generating the required clock on-chip, so that the user doesn't have to worry about it. This also may make it tough to determine what Trmw is, or it may require that Trmw = 2*Tcyc. Again, it depends on the part. Drop me a line of you have any more questions. -- Disclaimer: All spelling and/or grammar in this document are guaranteed to be correct; any exseptions is the is wurk uv intter-net deemuns,. Mike McManus Mike.McManus@FtCollins.NCR.COM, or NCR Microelectronics ncr-mpd!mikemc@ncr-sd.sandiego.ncr.com, or 2001 Danfield Ct. uunet!ncrlnk!ncr-mpd!garage!mikemc Ft. Collins, Colorado (303) 223-5100 Ext. 378