blw@acsu.buffalo.edu (brian l wybaillie) (12/02/90)
i have a circuit which uses a 74xx13 schmitt triggered dual 4 input nand in the following configurations; 74xx13 | | input ___________ v | ___|______ ___________ | | | |______| \ | | |_________| _______ \ | |____________| \____\__ )o-------- output |_______________| / |____________/ ___________ input ________________________| \ _____________| _______ \ | __________| \____\__ )o-------- output | | _______| / | | | |____________/ _|__|__|_ | | + Vcc can anyone tell me the difference, if any, these two circuits have with each other? the way i see it they are the same, the top one has all it's inputs tied to one which produces an inverted output. the bottom one is only dependant upon one of it's inputs since the other 3 are tied to Vcc. thus since it is a nand gate it will have the same outcome as the as the first circuit, (an inverter). is there any special reason for configuring it in the two different ways, i.e. faster responce, or sinking more current? thanks in advance for any cunstructive input. brian wybaillie ps. sorry for the poor graphics.
kilian@cray.com (Alan Kilian) (12/03/90)
In article <48711@eerie.acsu.Buffalo.EDU>, blw@acsu.buffalo.edu (brian l wybaillie) writes: > i have a circuit which uses a 74xx13 schmitt triggered dual 4 input > nand in the following configurations; > Edited.. > the top one has all > it's inputs tied to one which produces an inverted output. the bottom one > is only dependant upon one of it's inputs since the other 3 are tied to Vcc. > thus since it is a nand gate it will have the same outcome as the > as the first circuit, (an inverter). > is there any special reason for configuring it in the two different > ways, i.e. faster responce, or sinking more current? > brian wybaillie The logic producing the input for the first nand will have to drive 4 loads and the second one will only have to drive one load. I like the second one better. -Alan Kilian Cray Research, Inc. 655 F lone Oak Drive Eagan, MN 55121 kilian@cray.com
robf@mcs213k.cs.umr.edu (Rob Fugina) (12/03/90)
With 3 of the 4 inputs tied to Vcc instead of your input, it will draw less current from your input...that's what i've learned about 2-input nand gates in a couple of my EE classes. So the method of tying unused inputs to Vcc or ground is the preferred design. (An OR or a NOR would require unused inputs be tied to ground instead of Vcc). Rob...robf@cs.umr.edu
minsky@media-lab.MEDIA.MIT.EDU (Marvin Minsky) (12/03/90)
In article <1784@umriscc.isc.umr.edu> robf@mcs213k.cs.umr.edu (Rob Fugina) writes: >...the method of tying unused inputs to Vcc or ground is the preferred design. (An OR or a NOR would require unused inputs be tied to ground instead of Vcc). True. But let's see the actual pin diagram. On one side of the chip, Vcc is nearby, but on the other side, it is not. SO if the designer doesn't care about loading, you can simplify the PC layout, etc.
ssave@caen.engin.umich.edu (Shailendra Anant Save) (12/03/90)
In article <48711@eerie.acsu.Buffalo.EDU>, blw@acsu.buffalo.edu (brian l wybaillie) writes: > i have a circuit which uses a 74xx13 schmitt triggered dual 4 input > nand in the following configurations; > > 74xx13 > | > | > input ___________ v > | > ___|______ ___________ > | | | |______| \ > | | |_________| _______ \ > | |____________| \____\__ )o-------- output > |_______________| / > |____________/ > > > > ___________ > input ________________________| \ > _____________| _______ \ > | __________| \____\__ )o-------- output > | | _______| / > | | | |____________/ > _|__|__|_ > | > | > + Vcc > > > can anyone tell me the difference, if any, these two circuits have > with each other? the way i see it they are the same, the top one has all > it's inputs tied to one which produces an inverted output. the bottom one > is only dependant upon one of it's inputs since the other 3 are tied to Vcc. > thus since it is a nand gate it will have the same outcome as the > as the first circuit, (an inverter). > is there any special reason for configuring it in the two different > ways, i.e. faster responce, or sinking more current? I'd say that the fan-out of the gate that is producing the input would be used up (?) if method 1 is used. Also, in method 2, the schmitt sees a pure high voltage (5V) as opposed to a logic high of the input for the three inputs tied together. Hence faster? > > thanks in advance for any cunstructive input. > > brian wybaillie > > > ps. sorry for the poor graphics. Quite good graphics actually. :-) -- Physical: Shailendra Save, Logical: ssave@caen.engin.umich.edu 2303 Conger Baits II, UUCP: ...!umix!caen.engin.umich.edu!ssave Ann Arbor. MI 48109. Audible: 313-763-1627(H) 313-763-6466(O) ICBM: 42 33'W 83 71'N Fax: 313-747-1781 Eagles may soar, but weasels don't get sucked into jet engines. (For those who don't know, a weasel is a wolverine)
mark@mips.COM (Mark G. Johnson) (12/03/90)
(brian l wybaillie) asks whether it is preferable in a *Schmitt* *Trigger* NAND4 (74xx13) to construct an inverter by tying all 4 input pins to the input signal, or perhaps better to hook 3 of the 4 inputs to V+ and thereby load the input signal less. Shailendra and Marvin (and others) replied that input loading and board layout concerns should be the deciding factors. However they didn't address the effect of these connections upon the hysteresis of the gate {which is presumably the reason Brian is using a '13 instead of a '10}. The Internal Guts (TM) of the 74xx13 consists of four independent Schmitt trigger noninverting buffers, followed by a standard TTL NAND gate. So the four input signals don't mutually interact to set the logic threshold voltages. Each individual 74xx13 device might, of course, contain some miniscule fabrication mismatches that would render the trigger voltages on the 4 Schmitt buffers *slightly* different ... in which case the Shailendra circuit (3 to VCC, 1 to Input) would have a teencie bit less hysteresis than the Marvin circuit (4 to Input). It would however be unwise to depend upon this. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086 (408) 524-8308 mark@mips.com {or ...!decwrl!mips!mark}
jws@thumper.mlb.semi.harris.com (James W. Swonger) (12/03/90)
Paralleling inputs on 74{L,LS,S}13 gates does not increase the load current appreciably. There is only one pullup resistor on the input, which any of the diodes can pull down. The only loading penalty you pay is the pin capacitance which is probably insignificant. (The spec is usually 5pF but a real package is practically unmeasurable). The paralleled pins may in fact improve your delay by a nanosecond. The other point to consider is that some families of TTL do not respond well to having inputs tied to Vcc. LSTTL is OK, but I recall having S-series parts getting hurt. The TI "bible" indicates that only LS parts should be directly connected to Vcc; the other 4 (_, L, H, S) types should have a limiting resistor.
cgordon@vpnet.chi.il.us (Crash Gordon) (12/05/90)
>Author: [brian l wybaillie] > can anyone tell me the difference, if any, these two circuits have >with each other? The bottom circuit will load the driving circuitry less. This allows for greater fanout upstream, and/or lower propagation delay. The top circuit may be easier to prototype (by a miniscule factor), depending on your methods. ----------------------------------------------------- Gordon S. Hlavenka cgordon@vpnet.chi.il.us Disclaimer: Yeah, I said it. So what?
ken@csis.dit.csiro.au (Ken Yap) (12/05/90)
>> i have a circuit which uses a 74xx13 schmitt triggered dual 4 input >> nand in the following configurations; >> > > Edited.. > >> the top one has all >> it's inputs tied to one which produces an inverted output. the bottom one >> is only dependant upon one of it's inputs since the other 3 are tied to Vcc. >> thus since it is a nand gate it will have the same outcome as the >> as the first circuit, (an inverter). >> is there any special reason for configuring it in the two different >> ways, i.e. faster responce, or sinking more current? >> brian wybaillie > > The logic producing the input for the first nand will have to drive 4 loads >and the second one will only have to drive one load. It depends on the guts of the NAND gate. If you look at the circuit diagram of a typical N-input NAND gate there's only one resistor from Vcc to the base of the multi-emitter transistor so paralleling the inputs doesn't result in more current to sink. On the other hand, the capacitive load will certainly increase, with more protective diodes to ground so pulling up will be slowed. So yes, tie to Vcc if you can. I don't know if the Schmitt NAND has only one base for all the inputs.