dickson@ccu.umanitoba.ca (Jeff Dickson) (12/30/90)
I was recently approached for some suggestions regarding the design of a simple data logger. Since I don't have much experience with this problem I thought I'd see if anyone on the net could provide some guidance. The data logger is needed as a buffer between an A/D converter and the IBM PC expansion bus. The A/D will produce 2k of data at a high speed (I don't know how fast, but apparently it is not feasible to use the PC to capture the data directly). Can anyone suggest some sources for a circuit that will grab the data coming out of the A/D and allow the PC to fetch it at its own speed? I is there a high speed data logger / buffer IC out there that will make life simple? Thanks, Jeff Dickson dickson@eeserv.umanitoba.ca
ftpam1@acad3.alaska.edu (MUNTS PHILLIP A) (12/30/90)
In article <1990Dec29.204429.25744@ccu.umanitoba.ca>, dickson@ccu.umanitoba.ca (Jeff Dickson) writes... > > >I was recently approached for some suggestions regarding the design >of a simple data logger. Since I don't have much experience with >this problem I thought I'd see if anyone on the net could provide >some guidance. > >The data logger is needed as a buffer between an A/D converter and >the IBM PC expansion bus. The A/D will produce 2k of data at a >high speed (I don't know how fast, but apparently it is not feasible >to use the PC to capture the data directly). > >Can anyone suggest some sources for a circuit that will grab the >data coming out of the A/D and allow the PC to fetch it at its own >speed? I is there a high speed data logger / buffer IC out there that will >make life simple? > >Thanks, > >Jeff Dickson >dickson@eeserv.umanitoba.ca I had occasion to build one of these a couple of weeks ago. I used an ADC0820 A/D (8 bits, 2 uS and on board sample and hold) driving a 4 Kbyte FIFO (DS2012). A simple Schmidt trigger oscillator clocked the A/D on one edge and the FIFO inputs on the other. The outputs of the FIFO were connected to the printer port of an IBM PC. Good for about 10,000 samples per second, limited by the execution cycle of the PC. (I used a real original PC.) You could easily (1 PLD and a 74LS245 transceiver) adapt the circuit to the regular expansion bus and run it much faster. I used the FIFO to eliminate sampling jitter rather than sheer speed, as the PC was amply fast at 10 Ksamples/sec. The experiment required long (10 minutes) term sampling; FIFO capacity was of course only about 400 mS, long enough to cover the disk writes. Interestingly, I couldn't get a 3 section active filter (for antialiasing) stabilized so had to scrounge up some coils and capacitors for a truly ancient half-wave low pass filter. Sometimes ancient technology works best. Philip Munts N7AHL NRA Extremist, etc. University of Alaska, Fairbanks