steveh@tasman.cc.utas.edu.au (Steven Howell) (01/04/91)
Hi, I am about to employ a system for storing information electronically in one of our graphic systems. I intend on using 8x1Mb Simm modules, however the technique of controlling CAS and RAS is not familiar to me yet, and I wish to use a Hybrid controller to do the timming for me I have look up a couple of IC's that will do the job, but are $100 or so dollars, making it uneconomical (The chip is a 74S409). Does anyone have experience with this type of memory control, and would be happy to give me some suggestions on how I can interface 4Mbx8 to a 65c02 in a 4 bank configuration (The 6502 has only 11 available address lines for accessing memory, which means it can access only 1Mb of dynamic memory) Thanks in advance. Steve h
josephc@nntp-server.caltech.edu (Joseph I. Chiu) (01/05/91)
steveh@tasman.cc.utas.edu.au (Steven Howell) writes: > Hi, I am about to employ a system for storing information >electronically in one of our graphic systems. I intend on using 8x1Mb Simm >modules, however the technique of controlling CAS and RAS is not familiar >to me yet, and I wish to use a Hybrid controller to do the timming for me > I have look up a couple of IC's that will do the job, but are $100 or so >dollars, making it uneconomical (The chip is a 74S409). > Does anyone have experience with this type of memory control, and >would be happy to give me some suggestions on how I can interface 4Mbx8 >to a 65c02 in a 4 bank configuration (The 6502 has only 11 available address >lines for accessing memory, which means it can access only 1Mb of dynamic >memory) Not exactly an advice, but I've been thinking of the Apple II's lately, and this reminds me of an interesting fact about the original Apples. Wozniack (sp?) designed the system so that during the CPU's "off-bus" phase, the video control circuitry would take over the bus and read the memory off the video-ram in sequence (well, sort of -- it was actually interleaved). The side benefit that the sequential access of memory had on the system was that the video circuit generated each and every row-address so that an RAS refresh on the whole system was done as well... And all this with simple 74LS glue chips (imagine an SSI based video display!)... By the way, the 6502 has 16 lines of address for 65,536 bytes (64K of memory, as opposed to 1MB which requires 20 lines). To address 4Mb of memory, with 64K page at a time, would require a 6 bit mapping register. But since all I/O have to be memory mapped (6502's do not have separate I/O space), you are either looking at taking a chunk off each of the 64K page (probably about ~2-4K to cover zero-page, stack, and code) or mapping 32K pages for 7 bit mapping registers. Not exactly a fun thing to do... By the way, what you're probably looking at is latching A0-A11 on the memory's A0-A11, and A11-A14 plus M0-M6 on the memory's A0-A11 (for RAS and CAS, respectively). What you're doing is you're "latching" the first 12 bits of your address to select the "row" and then the last 12 bits of the address to select the "column" of the bit(s) you're interested in. All that's left is to refresh each row by address them at least once every 2 ms. (More often is good, but don't spend all your time on refreshing...) -- Joseph -- -- josephc@coil.caltech.edu ...Just another lost soul in the universe
josephc@nntp-server.caltech.edu (Joseph I. Chiu) (01/05/91)
josephc@nntp-server.caltech.edu (Joseph I. Chiu) writes: >By the way, what you're probably looking at is latching A0-A11 on the memory's >A0-A11, and A11-A14 plus M0-M6 on the memory's A0-A11 (for RAS and CAS, >respectively). What you're doing is you're "latching" the first 12 bits >of your address to select the "row" and then the last 12 bits of the address >to select the "column" of the bit(s) you're interested in. Oooops, sorry - just realized a mistake... Exchange row and RAS with column and CAS (and vice-versa). The memory is more efficient with RAS having the higher order address bits... Sorry about that. -Joseph -- -- josephc@coil.caltech.edu ...Just another lost soul in the universe