mlukka@lut.fi (Markku Lukka) (12/30/90)
Many thanks in advance for anyone who reads this article. As a hobbyist electronician I have come across a real problem. For a certain project, I would need an oscillator with digital, LOGARITHMIC adjusting (32-bit, 1000 x log) and a HUGE range, 1 kHz to 100 MHz. Is this at all possible? Then the next problem would be just to divide this signal into eight lines, so that the lines would pulse (change state, whichever would be the easiest) alternately, in order. I mean: Line 1,then line 2, then line 3, and at each input pulse from the oscillator the next line would be activated. This oscillator-divider pair would be used to control 8 memories, whose signals would be each in turn given to a D/A converter. BTW, is a VCO voltage/frequency ratio linear or what? Negative or positive? Please, if you read this message and know something about logarithmic frequency control, PLEASE! email to mlukka(at sign)kannel.lut.fi (at sign) doesn't seem to be available on this console. Sorry. mlukka(at sign again)kannel.lut.fi
bame@hpfcbig.SDE.HP.COM (Paul Bame) (01/03/91)
> As a hobbyist electronician I have come across a real problem. > For a certain project, I would need an oscillator with digital, > LOGARITHMIC adjusting (32-bit, 1000 x log) and a HUGE range, > 1 kHz to 100 MHz. Is this at all possible? Your "HUGE" range is probably not a big problem. You could probably use fairly standard PLL synthesis techniques. You might want to consider running an oscillator at, say 200-300 MHz and mixing it with 200 MHz to obtain 0-100 MHz. This way you get to use a VCO which covers a small range (1.5:1) which is not difficult. The incredibly precise logarithmic control may be a real pain - just consider the problem of accurately measuring 1 (log) bit in 32 bits with a frequency counter - you might need an expensive counter with a very long capture time to resolve 1KHz from 1KHz + 1 bit. You didn't mention how fast this thing is required to change frequency. > Then the next problem would be just to divide this signal into eight > lines, so that the lines would pulse (change state, whichever would be > the easiest) alternately, in order. I mean: Line 1,then line 2, then line 3, > and at each input pulse from the oscillator the next line would be activated. A fast shift register might do the trick - or (gasp!) a state machine. > This oscillator-divider pair would be used to control 8 memories, whose > signals would be each in turn given to a D/A converter. It sounds like you might get more help if you described what your design is supposed to do at a high level rather than a low level. It sounds like perhaps what you're doing could be solved other ways and maybe has been done before. -Paul "Spice is the Variety of Life" bame@hpfcbig.sde.hp.com N0KCL
mark@mips.COM (Mark G. Johnson) (01/06/91)
>> As a hobbyist electronician I have come across a real problem. >> For a certain project, I would need an oscillator with digital, >> LOGARITHMIC adjusting (32-bit, 1000 x log) and a HUGE range, >> 1 kHz to 100 MHz. Is this at all possible? In <6560003@hpfcbig.SDE.HP.COM> bame@hpfcbig.SDE.HP.COM (Paul Bame) writes: >The incredibly precise logarithmic control may be a real pain - just >consider the problem of accurately measuring 1 (log) bit in 32 bits with a >frequency counter - you might need an expensive counter with a very long >capture time to resolve 1KHz from 1KHz + 1 bit. You didn't mention how fast >this thing is required to change frequency. Just to consider it from another angle .... 32-bit frequency control requires what kind of resolution in _TIME_?? There are 2^32 = 4294967296 different frequencies. If let "R" stand for the ratio between frequencies, then 1kHz * (R ^ 4294967296) = 100 MHz, hence R = 1.00000000321667422079114998. The uppermost frequency is 100.0000000MHz ; the next lower frequency is (100MHz / R) = 99.999999678332578955584303 MHz. The _periods_ of the waveforms are: 100.000000000000000000000000 MHz: period = 10000000.00000000000 femtoseconds 99.999999678332578955584303 MHz: period = 10000000.03216674221 femtoseconds This would be exceedingly difficult to do, and even more difficult to verify / validate / certify. For example the timebase must have an accuracy of better than one part in 4294967296, while quartz crystals are typically 10 ppm (43000 parts in 4294967296). -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086 (408) 524-8308 mark@mips.com {or ...!decwrl!mips!mark}
minsky@media-lab.MEDIA.MIT.EDU (Marvin Minsky) (01/06/91)
In article <44553@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes: > >> For a certain project, I would need an oscillator with digital, > >> LOGARITHMIC adjusting (32-bit, 1000 x log) and a HUGE range, > >> 1 kHz to 100 MHz. Is this at all possible? I just bought a little pocket receiver, the ICOM R1. It is a triple superhet with tuning range from 100Khz to 1300 Mhz, in .5k increments. Works fine -- but I don't know what's inside it.
ftpam1@acad3.alaska.edu (MUNTS PHILLIP A) (01/06/91)
In article <44553@mips.mips.COM>, mark@mips.COM (Mark G. Johnson) writes... > > >> As a hobbyist electronician I have come across a real problem. > >> For a certain project, I would need an oscillator with digital, > >> LOGARITHMIC adjusting (32-bit, 1000 x log) and a HUGE range, > >> 1 kHz to 100 MHz. Is this at all possible? > >In <6560003@hpfcbig.SDE.HP.COM> bame@hpfcbig.SDE.HP.COM (Paul Bame) writes: > >The incredibly precise logarithmic control may be a real pain - just > >consider the problem of accurately measuring 1 (log) bit in 32 bits with a > >frequency counter - you might need an expensive counter with a very long > >capture time to resolve 1KHz from 1KHz + 1 bit. You didn't mention how fast > >this thing is required to change frequency. > > > >Just to consider it from another angle .... 32-bit frequency control requires >what kind of resolution in _TIME_?? There are 2^32 = 4294967296 different >frequencies. If let "R" stand for the ratio between frequencies, then > > 1kHz * (R ^ 4294967296) = 100 MHz, hence R = 1.00000000321667422079114998. > >The uppermost frequency is 100.0000000MHz ; the next lower frequency >is (100MHz / R) = 99.999999678332578955584303 MHz. The _periods_ of the >waveforms are: > > 100.000000000000000000000000 MHz: period = 10000000.00000000000 femtoseconds > 99.999999678332578955584303 MHz: period = 10000000.03216674221 femtoseconds > >This would be exceedingly difficult to do, and even more difficult to >verify / validate / certify. For example the timebase must have an >accuracy of better than one part in 4294967296, while quartz crystals >are typically 10 ppm (43000 parts in 4294967296). >-- > -- Mark Johnson > MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086 > (408) 524-8308 mark@mips.com {or ...!decwrl!mips!mark} The design could be easily (albeit expensively) done with one of the new direct digital synthesizers. For example, Stanford Telecom (408-980-5684) has a board in their catalog that does 0-110 MHz with 28 bits of frequency resolution. It costs $1750. With a 300 MHz clock, 28 bits yields 1.1 Hz steps. Philip Munts N7AHL NRA Extremist, etc. University of Alaska, Fairbanks
mcovingt@athena.cs.uga.edu (Michael A. Covington) (01/06/91)
In article <4733@media-lab.MEDIA.MIT.EDU> minsky@media-lab.media.mit.edu (Marvin Minsky) writes: >In article <44553@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >> >> For a certain project, I would need an oscillator with digital, >> >> LOGARITHMIC adjusting (32-bit, 1000 x log) and a HUGE range, >> >> 1 kHz to 100 MHz. Is this at all possible? > >I just bought a little pocket receiver, the ICOM R1. It is a triple >superhet with tuning range from 100Khz to 1300 Mhz, in .5k increments. >Works fine -- but I don't know what's inside it. It's almost certainly several different receivers (at least two) in one box. The usual wide-coverage (0.1-30 MHz) shortwave receiver has a local oscillator that goes from about 40 to 70 MHz, and a first IF around 40 MHz. This is then down-converted to 455 kHz and demodulated.
whit@milton.u.washington.edu (John Whitmore) (01/08/91)
In article <MLUKKA.90Dec29181404@kannel.lut.fi> mlukka@lut.fi (Markku Lukka) writes: >For a certain project, I would need an oscillator with digital, >LOGARITHMIC adjusting (32-bit, 1000 x log) and a HUGE range, >1 kHz to 100 MHz. Is this at all possible? Barely possible, and probably not very stable. There's an RCA application note (search in old RCA applications literature) on building a wide-range oscillator (roughly 1 Hz to 1 MHz) from their CA3080 transconductance amplifier. The basic principle is phase-shift oscillation, with the output impedance of the amplifier and the capacitive load providing the phase shift. The programming current is the frequency control. This programming current goes into the base of a grounded-emitter transistor, so the Vbe on that transistor is a logarithmic voltage signal (and with an op amp, you can use that as the logarithm adjusting generator you refer to; exercise for the reader). In the 1977 RCA linear databook, the oscillator is described in Fig. 23, p. 169 (part of the CA3080 data sheet). As a practical matter, you'll need a thermostat on the logarithm transistor (because the transfer curve is temperature dependent as well as logarithmic), and your noise (a few nanovolts) might NOT be negligible on the voltage-control input. The stray capacitance of each amplifier stage will affect the frequency (drift is likely). Normally, wide-range VCOs use several narrow-band VCOs and switch from one to another (for TV, three bands suffices). >Then the next problem would be just to divide this signal into eight >lines, so that the lines would pulse (change state, whichever would be >the easiest) alternately, in order. I mean: Line 1,then line 2, then line 3, Well, that's possible if you use an eight-stage phase shift network (three is more typical). Alternately, you can consider a higher-frequency phase-locked signal with a 'twisted ring' counter. Eight D flip-flops with each Q connected to the next D, and the final /Q connected to the first D, all clocked by 8x the highest frequency you want, would do it. That means 800 MHz clock rates, just barely possible with fast logic. GaAs or ECL of course (TTL is hopeless at this frequency). John Whitmore