[sci.electronics] Problem interpreting M68HC11 documentation

ma@stl.stc.co.uk (01/08/91)

I am using the Motorola M68HC11 in an amateur project, but am having
great difficulty in decoding the documentation (the reference manual,
and the technical summary for the version I am using, MC68HC11A0).  I
wonder if others on the net have experience with this processor, and
could enlighten me.

I am using an external CMOS RAM as program memory, and using the
processor's bootstrap mode to load the RAM from a PC via the serial
line.  I will probably replace the RAM with an EPROM once I have
finalised the software.

My problem is that it is unclear what state the data bus is in when
the processor is reset in bootstrap mode, and if I need to take any
precautions to prevent contention between the bootstrap ROM and
external RAM which occupy the same address.

The manual states two things, in different places.  (1) It states
that bootstrap mode is a special version of single chip mode, in which
ports B and C are used as programmable peripheral ports.  This would
mean that the multiplexed low address/data bus will start off in input
mode, and the high address bus will be set to zeros.  (2) It also
states that the default value of the IRV (internal read visibility)
bit in the HPRIO register is 1 in the bootstrap mode, and that when
IRV is set internal reads cause the external data bus to be driven
with the data read internally (for debugging purposes).  This could
lead to contention between the internal bootstrap ROM, and external
RAM at the same address.

Can anyone enlighten me which is correct, (1) or (2)?  The processor I
have seems to follow (1), but can I be sure that all future processors
will keep to interpretation (1)?

As a supplementary question, I assume that I need to put pull-up
resistors on the data bus, to prevent excessive currents in CMOS bus
receivers if the bus floats in an intermediate logic state.  However,
because my system is battery powered, I do not want excessive
dissipation in these resistors.  Is it reasonable to use very high
values (perhaps 1 Meg)?  Alternatively, is it reasonable to bootstrap
the load resistors (in the electronic, rather than software sense!)
with a circuit like:

                                 |\ 
                                 | \        10K
            To data bus  <---+---|  >------/\/\/\---+
                             |   | /                |
                             |   |/ Non-inverting   |
                             |         buffer       |
                             |                      |
                             +----------------------+

I've never seen such a circuit used (although I must admit that I
specialise in software, not hardware!) but it does seem to be a neat
way of minimising dissipation in the pullup/pulldown resistors while
keeping the bus in a legal state.

Perhaps you could reply by mail -- I will summarise any replies I get
to the net.

Regards

Melvin Anderson      <ma@stl.stc.co.uk>

STC Technology Ltd., London Road, Harlow, Essex, England.

ma@stl.stc.co.uk (Melvin Anderson) (01/14/91)

A few days ago I asked if anyone could clarify a question I had with
the documentation for the M68HC11, and said I would post a summary for
others who may be interested.

Thanks for the replies.  My first problem was whether the external bus
is driven when the processor is reset in special bootstrap mode, my
confusion being caused because the IRV bit is initially set in the
HPRIO register.

Rand Gray <rand@zeta.sps.mot.com> of Motorola MCU Development Systems
was kind enough to clarify:

   IRV is active in SPECIAL TEST mode only, which is not what you are
   booting with.  You correctly surmise that there will be no
   contention.

Secondly, I wondered about whether I needed to terminate the CMOS
tri-state data bus, about which Rand continues:

   Unterminated inputs and inputs which are tri-stated should definitely
   be pulled up.  If you use a CMOS or HCMOS static RAM, you could easily
   get away with 470k pullups, as the typical leakage of the inputs is
   much less than the 1 microamp max leakage specified in the HC11 spec.

   A 10-pin SIP resistor network with common-bus circuit has pin 1 as
   common, and 2 through 10 available as pullups (or pulldowns).

Thanks for the help.  I am pleased to say that after a few evenings
with a soldering iron the processor seems to be working nicely.  I
plan to use it as the heart of a clock to pick up the standard time
and frequency transmission from Rugby, here in England.  Hence my wish
to keep power consumption to a minimum so I can run it using a
battery.

Thanks again,

Melvin Anderson      <ma@stl.stc.co.uk>

STC Technology Ltd., London Road, Harlow, Essex, England.