whit@milton.u.washington.edu (John Whitmore) (01/19/91)
In article <1991Jan16.161646.9446@athena.cs.uga.edu> mcovingt@athena.cs.uga.edu (Michael A. Covington) writes: >In article <1991Jan14.205104.2829526@locus.com> dana@locus.com (Dana H. Myers) writes: >> >>Since we are assuming the power is disspated in capacitance, we'll >>use the simple form of capacitive reactance: > Er... Power is not dissipated in capacitance. No such thing. > Only resistance can dissipate power. > >A CMOS chip dissipates power resistively while transitioning from one >state to the other, and while charging the input capacitance of another >chip. (That's how capacitance got into it... the capacitance does not >dissipate power, but it provides current flow through a resistance.) OK so far, but the formula is very important here; I = V * (1/R) * exp(- t/(RC)) power= I^2 *R = V^2 * (1/R) * exp(-2t/(RC)) >The time taken to make a transition, and the time taken to charge an >input capacitance, are constant for any given set of chips. i.e. RC = constant? Completely unimportant. For logic, RC is ALWAYS much smaller than Fclock; if not, the noise margin would be compromised. The total power after many RC times, by the formula above, comes out to Energy dissipated in resistor = integral(t=0 to t= infinity) power* dt = V^2 * C * 1/2 In a very real sense, then, the only way to lower the power dissipation of the chip is to lower the number of transitions (lower the clock frequency) or lower the gate capacitance, or lower the power supply voltage. Calling this term in the power requirement 'capacitive losses' is both descriptive and informative. It's independent of the value of the MOSFET output resistance, so calling it 'resistive losses' would be obfuscatory. Yes, the losses DO occur in a resistor. No, the losses are not related to the magnitude of some resistance. John Whitmore whit@milton.u.washington.edu