eeyore@cs.qmw.ac.uk (Mark Anthony Brown) (02/07/91)
\documentstyle[hplj]{article}
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\begin{document}
\title{The PMBUS}
\author{Revision 5}
\date{December 1988}
\maketitle
\section{General}
The {\sc pmbus} was developed in 1982 to address the need for a fast, low-cost
system bus for the emerging 16/32-bit processors. Today it is in use in
commercial products from various companies, ranging from workstations to
embedded controllers.
The {\sc pmbus} specification is completely public-domain. It may be copied and
distributed freely, and may be implemented for any purpose without
restriction.
\section{Introduction}
The {\sc pmbus} is a modular, expandable bus system for 16 and 32 bit
micro systems. Although designed primarily for the MC68000, it is
compatible with most current and projected 16 and 32 bit micros.
The bus protocol and timings are based closely on those of the 68000,
as this makes implementation on a 68000 simple, while most other
processors can be interfaced with some simple logic.
The {\sc pmbus} is implemented on three levels, and uses a double-size
(standard or extended) Eurocard format with single or dual DIN 41612
(A+B) connectors. Level 0, using the lower connector only, provides a
low-cost approach for systems with a memory space of up to 128 Kbytes,
and three separate prioritized interrupts. It is directly
up-compatible to level 1, which provides a full 16 Mbyte address
range, eight levels of interrupt, prioritised DMA, multi-processor
systems and full virtual memory, using two DIN connectors.
Level 2 provides true 32 bit operation. Dynamic data bus sizing is provided,
allowing Level 0/1 hardware to be accessed at its proper location, and
in particular allowing Level 0/1 devices to appear 32 bits wide, so that
Level 0/1 memories etc can be used, albeit with a speed penalty since twice
as many accesses are required.
\section{Implementation}
Since the {\sc pmbus} is based around the bus protocol and timings of the 68000,
some familiarity with the 68000 bus is assumed; this document will not
describe the 68000 bus in detail. Full timings are given, however, as these
are system-level timings taking into account such things as buffer propagation
delays.
\subsection{Structure of the PMBUS}
The {\sc pmbus} requires only a simple backplane, running all lines in parallel to
all cards. A simple groundplane should be used; a normal double-sided PCB
provides a perfectly adequate structure with the tracks on one side and a
groundplane on the other. Unlike many other bsuses, the {\sc pmbus} does {\em not\/}
require elaborate multilayer PCBs.
The {\sc pmbus} also avoids complex and costly termination schemes. The {\sc data}
lines, which do not require ultra-fast, ringing-free edges, are normally
driven with standard {\sc lsttl} devices, while the address and control lines
use high-threshold {\sc cmos} devices to minimise susceptibility to noise. For
these lines, simple series termination (22$\Omega$ typical) will suffice, and is
only required on cards capable of assuming bus mastership. Some slower {\sc pmbus}
implementations dispense with the terminations altogether.
One board (usually the main CPU) is designated as overall bus controller, and
generates the clocks CLK and E. Other potential bus masters, such as other
CPUs and DMA peripherals, are designated DMABMDs\footnote{Direct Memory Access
Bus Master Devices.}.
\subsection{Logic Levels and Electrical Considerations}
To maximise the noise immunity of critical signals, some lines (addresses and
some control lines) are noted as 'H' (High threshold) in the definition
below; these are to be driven to {\sc cmos} logic levels (e.g. by 74HCT or 74ACT
series drivers) rather than {\sc lsttl} levels, which are acceptable for
all other signals. Receivers may use {\sc cmos} or {\sc ttl} thresholds, at
the card designer's discretion, but in the interests of reliability,
cards which cannot tolerate ringing or other noise on signal transitions
should use {\sc cmos} thresholds. {\sc fttl} is acceptable in many
applications, as it has significantly more noise immunity than {\sc lsttl},
although {\sc cmos} levels are to be preferred.
When designing, remember that 74HCT and 74ACT
devices have {\sc ttl}, not {\sc cmos}, input thresholds.
The drive requirements are as follows: Open-collector lines (*1 below) may be
driven by standard-drive (8mA) {\sc lsttl} or {\sc cmos}
open-collector gates; all non-open-collector lines must be
driven with high-drive (e.g. '244, '541, '245, '374 etc) drivers of the
appropriate\footnote
{Note that there is no objection to
{\em driving\/} the {\sc ttl}-level lines to CMOS levels, however.}
({\sc cmos} or {\sc ttl}) family\footnote
{When the 74AC/74ACT family is used, any device type may be used, as all
outputs have 24mA drive.}.
RESET' on the bus is bidirectional and therefore unbuffered (from a 68000
CPU); HALTO' is buffered on the CPU card. Other open-collector lines are inputs to the
microprocessor and should in general not be buffered to maintain speed, with the
exception of BGAK', which when asserted tri-states all non-open-collector lines
except CLK, BG', and E, and must therefore be buffered so as to present
a low capacitive load to the bus rather than controlling numerous
buffers directly.
The open-collector lines should be terminated at the master CPU card by the following
resistances to +5V:
\begin{tabular}{p{1in}ll}
& RESET': & 4k7\\
& DTAK', BERR', VPA', BR', BGAK', SIZE': & 560$\Omega$ \\
& I1'--I7', HALTI', WAIT': & 2k2
\end{tabular}
The 560$\Omega$ pull-ups ensure a quick rise time for those signals which require it,
even with the capacitance of a large backplane with many cards. Additionally,
the lines INTAK', IOS' and HALTO' should be pulled up with 4k7 resistors on
the master CPU card so that DMA devices which do not require these lines can leave
them undriven without them becoming spuriously asserted.
\subsection{PMBUS LEVEL 0 -- Bottom connector}
\begin{tabular}{llll}
\underline{Pin}&\underline{Function}&&\underline{Notes}\\
AB 1/2 & GND &&\\
AB 31/32 & +5V &&\\
AB 3 & +12V &&\\
A 4 & PWRFAIL' &*6H & Power supply failure warning \\
A 5 & -12V &&\\
A 6--21 & D0--D15 & & 16 bit data bus (bidirectional)\\
A 22 & RADS & H & Active high address strobe for lower 128kb\\
A 23 & UDS' & H & Upper data strobe\\
A 24 & LDS' & H & Lower data strobe\\
A 25 & DS' & H & Data strobe\\
A 26 & RESET' &*2 & Reset input/output\\
A 27 & HALTI' &*1 & Processor halt input\\
A 28 & R/W' & H & Write strobe\\
A 29 & AS' & H & Address strobe for any access\\
A 30 & DTAK' &*1 & Data transfer acknowledge\\
B 4 & (reserved)& & (Unused on revision 5)\\
B 5 & CLK & H & Processor clock output\\
B 6--21 & A1--A16 & H& Reduced address bus\\
B 22 & BERR' &*1 & Bus error signal\\
B 23 & IOS' &*3H & Address strobe for I/O page\\
B 24 & VPA' &*1 & Request for 6800-type synchronous bus cycle\\
B 25 & VMA' & H & Shows 6800-type cycle in progress\\
B 26 & E & H & Clock for 6800-type cycles\\
B 27 & I1' &*1 & Priority 1 interrupt (maskable)\\
B 28 & I2' &*1 & Priority 2 interrupt (maskable)\\
B 29 & I7/NMI' &*1 & Non-maskable priority 7 interrupt\\
B 30 & INTAK' & H & Interrupt acknowledge
\end{tabular}
\subsection{PMBUS LEVEL 1 -- Top connector}
\begin{tabular}{llll}
\underline{Pin}&\underline{Function}&&\underline{Notes}\\
AB 1 & GND &&\\
A 2 & BGAK' & *1 & Bus grant acknowledge\\
A 3 & BG' & H & Bus grant\\
A 4 & BR' & *1 & Bus request\\
A 5--7 & FC0--2 & H& Processor function codes\\
A 8--11 & I3--6' & *1 & Maskable interrupts\\
B 2--8 & A17--A23 & H& Extended address bus\\
B 9 & HALTO' & H & Active if HALTI' low or CPU halts\\
B 10 & WAIT' & *1,4 & Disables nonresponding device timer\\
B 11 & REFCLK & *4H & Refresh control line for d-RAM controller\\
B 21--27 & DP1--7' & *1 & DMA priority signals
\end{tabular}
\subsection{PMBUS LEVEL 2 -- Top connector}
\begin{tabular}{llll}
\underline{Pin}&\underline{Function}&&\underline{Notes}\\
A 12--19 & D16--D23 & & Extended data bus\\
A 20 & XLDS' & H & Data strobe for D16--23\\
A 21 & SIZE' & *1,5 & Indicates 32--bit wide device addressed\\
B 12--19 & D24--D31 & & Extended data bus\\
B 20 & XUDS' & H & Data strobe for D24--31
\end{tabular}
\begin{flushleft}
{\large\bf Notes}
\end{flushleft}
\begin{itemize}
\item[{\bf *1}] Open collector common line. Any device may operate line as required.
\item[{\bf *2}] Resets CPU if HALTI' is also low. Also resets external devices.
\item[{\bf *3}] Defined on CPU card; goes low when AS' is active and address is
within a 256 word (512 byte) block reserved for I/O devices. This may
be mapped into the main address space or be a separate space, according
to the processor used and the designer's preference.
\item[{\bf *4}] Optional extension. These lines are reserved for the purpose indicated
but are frequently not implemented. If your design uses them, proceed
with caution.
\item[{\bf *5}] The {\sc pmbus} is by default 16 bits wide (although byte-wide devices will
ignore half the bus), and even if a 32 bit processor is installed, bus
cycles are by default 16 bits. If a device capable of 32 bit operation
is addressed, it pulls down SIZE' (no later than it asserts DTAK') to
show it is using the entire 32 bit data bus (gated by XUDS' and XLDS'
from the processor). Note that for a processor using 68020-style databus
ordering, on a 32 bit transfer, bus lines D0--D15 will actually carry the {\em
more\/} significant 16 bits of the data, while D16--D31 will carry the {\em
less\/} significant word. In other words, {\sc pmbus} data lines 0--15 correspond
to 68020 data lines 16--31 and {\em vice versa}\/.
\item[{\bf *6}] PWRFAIL' is a signal from the system power supply unit which drops
low at least 5 milliseconds before the {\sc pmbus} power rails fail when the
machine is switched off or disconnected from the mains. In addition, it
must not go high until at least 200 milliseconds after the power rails
reach their proper voltages when the machine is powered up. The line is
driven by a current source with a pull-down resistor, and must {\em not\/} be used to drive
{\sc ttl} gates ({\sc cmos} is OK). The line is {\em not\/} intended as a system reset, but to protect
devices such as battery-backed memory from corruption.
\end{itemize}
\subsection{Derivation of signals from a 68000 microprocessor}
The following logic equations define the lines listed below:
\begin{itemize}
\item DS' = UDS'.LDS'
\item INTAK' = ([AS']'.FC0.FC1.FC2)'
\item RADS = (AS'+A17+A18+A19+A20+A21+A22+A23)'
\end{itemize}
In addition, IOS' is derived by gating address lines and AS' (or RADS) to
select a specific 256-word (512-byte) block of memory. By convention this is
at \$1000 -- \$11FF, but may be located anywhere in the processor's address
space.
\section{Timing Requirements}
All cards must conform to these specifications. Signals are quoted
for 6, 8 and 10 MHz CLK frequencies, although the vast majority of {\sc pmbus}
systems today run the bus at 10 MHz. The slower speeds are regarded
as obsolescent and are not recommended for new designs.
Remember that
these timings refer to an entire card, and the signal names refer to
the {\sc pmbus}, not the microprocessor chip itself, so allow for any buffers
{\em on the card in question\/} only. All timings are in nanoseconds.
\subsection{CPU Cards and DMABMDs}
\begin{tabular}{lrrrc}
\underline{Parameter}&\underline{6\sc MHz}&\underline{8\sc MHz}&\underline{10\sc MHz}&\\
Address valid to AS' low & 35 & 30 & 20 &min\\
Address hold after AS' high & 40 & 30 & 20 &min\\
MPUs AS' low to RADS high & 48 & 48 & 38 &max\\
MPUs AS' high to RADS low & 48 & 48 & 38 &max\\
MPUs UDS'/LDS' to DS' (high or low) & 38 & 38 & 16 &max\\
MPUs AS' to INTAK' (high or low) & 50 & 50 & 40 &max\\
MPUs AS' low to IOS' low & 100 & 100 & 80 &max\\
MPUs AS' high to IOS' high & 90 & 90 & 70 &max\\
Data setup time before UDS'/LDS' low (write) & 30 & 30 & 20 &min\\
Data hold time after UDS'/LDS' high (write) & 40 & 30 & 20 &min\\
Address/control buffer prop delay (for 68000) & 20 & 20 & 8 &max\\
Data buffer prop delay (for 68000) & 12 & 12 & 12 &max
\end{tabular}
\subsection{Peripheral Cards}
\begin{tabular}{lrrrc}
\underline{Parameter}&\underline{6\sc MHz}&\underline{8\sc MHz}&\underline{10\sc MHz}&\\
DS' low to DTAK' low for full speed reads & 120 & 75 & 64 &max\\
DTAK' release time from DS' high & 120 & 80 & 74 &max\\
DTAK' release time from UDS'/LDS' high & 140 & 100 & 82 &max\\
Read access time from RADS (full speed) & 263 & 180 & 135 &max\\
Read access time from UDS'/LDS' (full speed) & 293 & 210 & 165 &max\\
DTAK' low before data valid (slow read cycle)& 102 & 72 & 57 &max\\
Strobes inactive to data bus tri-state & 150 & 120 & 85 &max\\
IOS' high to VPA' high & 68 & 28 & 20 &max\\
AS' high to VPA' high (alternative) & 140 & 80 & 74 &max
\end{tabular}
\section{Further Notes}
\subsection{Bus Error Timer}
The CPU card contains a timer which is started when AS' is low,
and if the cycle has not terminated (ie. AS' is still low) after
(e.g.) 10 $\mu$s, asserts BERR' to terminate the bus cycle in the event of
a non-responding device or an access to unpopulated address space. The
level 1 signal WAIT' holds this timer at zero when asserted, to allow
long cycles if necessary (although these are not advised, and may
prevent use of dynamic {\sc ram}). Note that WAIT' is optional.
\subsection{Pull Ups (68000 processors)}
Output lines on the processor chip which are tri-state (other
than address and data pins) should be pulled up with a 10k resistor
before buffering to prevent inadvertent assertion when the lines are
in the off-state.
\subsection{Tri-state Control}
In a level 0 system, the CPU card drives the bus all the time.
In a level 1 or 2 system, (with bus arbitration), the CPU card buffers
are disabled when BGAK' is low. Note that BGAK' will require a buffer
to drive the many control inputs. The following lines are {\em not\/} affected
(ie. turned off) by BGAK': CLK, BG', E, RESET'.
\section{DMA on the PMBUS}
Any card capable of taking bus mastership and performing DMA is
termed a DMA Bus Master Device (DMABMD). When in control of the
bus, a DMABMD must drive all of the following lines: AS', UDS', LDS', DS', RADS, R/W',
VMA', and all data and address lines. INTAK', IOS', HALTO' are pulled up on the CPU
card with 4k7 resistors, so they can be ignored by DMABMDs which do not need them.
The DMA mastership arbitration is performed in a distributed manner: each DMABMD
has its own arbitration unit, and these contend with each other via the
DP1--7 lines for mastership. (DP7' has the highest priority; only one DMABMD
is allowed on each priority).
The arbitration rule is ``first come first served'',
except when more than one DMABMD is requesting mastership simultaneously, in
which case the requests are satisfied in priority order. Once a DMABMD has
control of the bus, it cannot be forced to relinquish it, even by a higher
priority DMABMD, but re-arbitration will occur as soon as the present master
relinquishes the bus.
The arbitration state machine is described below, although most
implementations use a commercially-available two-chip semi-custom IC set to perform the entire function, including
buffer control and a simple 'request-proceed' interface to a DMA device.
\subsection{Arbitration Sequence}
All state transitions (at the bus itself) must take place between 0--30 ns
after the rising edge of bus CLK. The state machine is therefore fully
synchronous.
When the DMABMD wishes to request the bus, it waits until BR', BG' and BGAK'
are all high, then asserts BR' and its own DP{\em n}\/' line simultaneously.
On the first rising edge of CLK after BG' has gone low (indicating the start
of arbitration), the DMABMD latches the output of its priority network
(signal MINE+, which by definition will only be true for the highest-priority
DMABMD currently requesting the bus). On the next CLK rising edge after AS' and
DTAK' both become high, the DMABMD
with MINE+ high asserts BGAK', turns on its tri-state buffers and takes over the
bus. When they see BGAK' asserted, all DMABMDs simultaneously cancel their
BR' and DPn' signals.
When the last cycle is complete and DTAK' has been cancelled, the bus master
cancels BGAK' and turns its tristate buffers off.
\end{document}
--
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Mark A. Brown |
Research Student | land line: +44 71 975 5220
Department of Computer Science | JANET: eeyore@uk.ac.qmw.cs
Queen Mary & Westfield College | UUCP: eeyore@qmc-cs.UUCP
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