tran@elaine14.Stanford.EDU (Hy Tran) (03/09/91)
I have two signals: Call them S1 and S2. S1 is at frequency F1; S2
is at frequency n*F1 (say, 7*F1). The frequencies are locked, but not
in phase.
_ _
______| |_______________________________________| |_________ S1
_ _ _ _ _ _ _ _
__| |____| |____| |____| |____| |____| |____| |____| |____ S2
What I want to do is to stretch out the pulse of S1, so that its
falling edge is synchronized with the next S2 falling edge: (i.e.
obtaining an S3 like this)
_ _
______| |_______________________________________| |_________ S1
_ _ _ _ _ _ _ _
__| |____| |____| |____| |____| |____| |____| |____| |____ S2
____ ____
______| |____________________________________| |_______ S3
I think that can be done with a flip-flop, or some sort of logic
gate(s), but I'm more an analog type of person. Suggestions, please?
Thanks,
Hy
tran@sun-valley.stanford.edu
P.S. Oh, if it helps: The frequencies I'm looking at are on the order
of 0.5 to 20 kHz.dbell@cup.portal.com (David J Bell) (03/12/91)
Easy.... You'll need two inverters, unless your S1 and S2 are available as negative-going pulses, and a single type-D flip/flop. (74LS74, or many equivalents is fine.) |\ S1 --------| >o--------------- |/ | o ------- | S | ------|D Q|------------> S3 | | | |\ (Gnd) V | | S2 --| >o-----------------|>C | |/ | | |_____| How it works: S1 going to a HI level causes the SET input of the D flip/flop to be activated, bringing Q HI. Falling edge of S2 causes a rising edge into the CLK input, which causes the LO input to D to propagate to the Q... This presupposes that S1 is never wide enough to overlap the falling edge of S2... Dave dbell@cup.portal.com