clldomps@cs.ruu.nl (Louis van Dompselaar) (03/11/91)
Can anyone tell me how the refresh is done on the 1Mbit D-RAM chips? I saw a small datasheet which only stated which types of refresh were supported, but it didn't say how to get them working I'm particularly interested in how to use the built-in refresh counters Louis clldomps@praxis.cs.ruu.nl
astevens@acorn.co.uk (Ashley Stevens) (03/13/91)
In article <1991Mar11.123454.22302@cs.ruu.nl> clldomps@cs.ruu.nl (Louis van Dompselaar) writes: >Can anyone tell me how the refresh is done on the 1Mbit D-RAM chips? >I saw a small datasheet which only stated which types of refresh >were supported, but it didn't say how to get them working >I'm particularly interested in how to use the built-in refresh counters As you know, refresh is done on a row by a Ras cycle. ie each time ras goes low, the address on the address inputs is refreshed. This can be as a refresh cycle only (ras only refresh), or part of another cycle. (eg a read cycle, write cyles, read-modify-write etc). However, in addition to this method, there is also cas-before-ras refresh, that you allude to. In this mode, an internal counter is used as the row address for a refresh operation. A cas-before-ras refresh cycle is instigated by taking cas low before ras (the opposite to a normal cyle). There is then a period where both are low, and then they go high again, though not necessarily at the same time. Each time one of these cycles is performed, the row given by the internal refresh counter is refreshed, and the internal refresh counter is incremented. As I'm sure you're aware, there a multitudes of timing restrictions etc, so you should really get a good data sheet on the device you're using before trying to do anything with it. ___________________________________________________________________ Ashley Stevens astevens@acorn.co.uk Acorn Computers, 645 Newmarket Rd, Cambridge, UK. Tel.(0223) 214411