CPS@cup.portal.com (CHRIS PATRIC SMOLINSKI) (03/15/91)
Help! I'm trying to use 5 74192 BCD counters in a PLL freq synth
circuit. The problem I'm having is that as I increase the input
frequency, I begin to "lose" chips. Let me explain. At a frequency of
say 1 mhz, everything is fine. As I increase the frequency, first the
highest counter fails to assert the borrow output (I am preloading the
counters with an initial value (the frequency I want) and counting down).
As I increase the frequency, the "failure" occurs earlier in the counter
chain. However, the "failed" counter is still counting itself (the four
outputs still show the chip is counting). And, if I replace the chips
with 74193s (4 bit counters), everything is fine.
Any dieas?
^ideas
- CHRISgrege@gold.gvg.tek.com (Greg Ebert) (03/20/91)
In article <40157@cup.portal.com> CPS@cup.portal.com (CHRIS PATRIC SMOLINSKI) writes: >Help! I'm trying to use 5 74192 BCD counters in a PLL freq synth >circuit. The problem I'm having is that as I increase the input >frequency, I begin to "lose" chips. > [...] Despite being labeled 'synchronous' in the data sheet, these devices are *NOT* synchronous counters when you cascade them. The reason is that internal to the chip, the "BORROW" and "CARRY" outputs are combinatorial. A truly synchronous system ties the same constantly-running clock to EVERY flip-flop with no gating whatsoever in the clock circuit other than the guts of each flip-flop. I don't know the specifics of your circuit, but I'm guessing that you preload a count-value when the counters decrement to zero. Counters and decoders are notorious for generating glitches as they quiesce. But, fear not. You can probably pipeline your decode by sticking a register between the decoder output and the "LOAD" pins on the counters. Your divider will be off by 1 'tick' unless you decode state 1 instead of state 0. You can compute the maximum input frequency by adding-up the propagation delays in the borrow & carry chains (26nsec max per device for 74192/74193), except for the last device in the chain. Add to this time it takes to generate your decode, and the UP/DN-to-Q delay of the last counter (47ns).