steveh@tasman.cc.utas.edu.au (Steven Howell) (04/25/91)
Evening peoples. I have been studying various memory boards an have noticed a common difference. on some boards there are resistor in series with the data and CAS RAS data lines, whilst others do not have them. The resistance of these current limiting devices is only 68ohms! does anyone know why they are there. Why can't you directly interface the bus to the chip, like some have done. Is it bad? What would happen if they were removed and replaced with direct links. can someone please enlighten me on this topic. thanks in advance steve h
robertb@june.cs.washington.edu (Robert Bedichek) (04/26/91)
In article <steveh.672590456@tasman> steveh@tasman.cc.utas.edu.au (Steven Howell) writes: > I have been studying various memory boards an have noticed a >common difference. on some boards there are resistor in series with the >data and CAS RAS data lines, whilst others do not have them. > >The resistance of these current limiting devices is only 68ohms! > >does anyone know why they are there. Why can't you directly interface the bus >to the chip, like some have done. Is it bad? >What would happen if they were removed and replaced with direct links. >can someone please enlighten me on this topic. These are series-termination resistors, to match the impedance of the driver to its load. Series termination works well in memory systems which are high capacitive and are driven at a single point. If don't match the impedances, you will get ringing and may have to wait for the round-trip time on the lines for a reliable signal. So if your lines are short and/or you don't mind waiting the couple of nanoseconds of round trip reflection time, you can do without the termination resistors. Note that the value is not always 68 ohms, it depends and is often lower. If the under-overshoot on the ringing is really large perhaps you could damage the DRAMs? I don't know. A couple of years ago the ringing could cause CMOS latch-up, but I think the semi companies have licked that problem. There are a number of papers on how to design memory systems, send me email if you would like a reference (I don't have them handy now). Robert Bedichek robertb@cs.washington.edu