probst@iiic.ethz.ch (Probst) (05/10/91)
I'm trying to convert 50Hz from the power line into 102.4 kHz using
a PLL. The 102.4 kHz are feed into a dual-slope A/D-converter (ICL7109,
12bit resolution). By generating the A/D-converter clock from the power
line, I would get maximum power line rejection.
The problem is (could it be different?) that the PLL doesn't lock...
I've built up the circuit as proposed in the Motorola datasheet of the
MC14046B (= CD4046B, HEF4046 etc.) with the second low-pass filter (two
resistors and one capacitor) and using the second phase comparator
(which switches on rising edges). I've set the VCO-output range from 40
kHz to about 350kHz, but I've also tried it with a narrow range from 80kHz to
120kHz.
To calculate the low pass filter components, I've tried Motorola's
method, and other methods which I found in a book about PLL-Desgin.
The result was always the same, the output frequency went to or near to
the maximum VCO frequency, preferably 2, 2.5 or 3 times the requested
output frequency of 102.4 kHz with an additional phase shift.
Reducing the divide factor of the feed-back to two (Output: 100Hz)
and recalculating the filter didn't change anything.
I've examined the output of the phase comparator and found that it
didn't work as shown in the datasheet: I connected the 50Hz to input A
and a variable clock to input B. When I increased the clock at input B
to about 51Hz and above, I couldn't see any negative going pulses at the
output of the comparator (as it should in order to reduce VCO-input voltage).
The first occurance of negative ("slow down") pulses I recognized at
about 100Hz !! (I've tried this with different chips.)
What I understand so far is, that it is critical to have a low reference
input frequency to the PLL. But it seems to be possible to do the job,
as shown in the book "The Art of Electronics", p. 1xx.
Does someone know how to design such a PLL? Please help me.
Thanks in advance,
-Urs Probst probst@iiic.ethz.ch, Zurich, Switzerland.