[sci.electronics] Distinguishing between logic state and tri state

sashahi@uokmax.ecn.uoknor.edu (Sandeep Shahi) (06/04/91)

   Can anybody suggest a circuit which can separate a logic(0 or 1)
from a tri state.
		he output of such a circuit is to be read by the host
for further action

Thanx
ss

stevem@specialix.co.uk (Steven Murray) (06/04/91)

sashahi@uokmax.ecn.uoknor.edu (Sandeep Shahi) writes:


>   Can anybody suggest a circuit which can separate a logic(0 or 1)
>   from a tri state.
>   The output of such a circuit is to be read by the host
>   for further action

My suggestion is pull the signal to an 'indeterminate' state with
a resistor to ground and a resistor to +5v, then put a 'window comparator'
on the signal to see when it has reached this voltage.
Precise values will depend on the circuit, but for a typical TTL application,
you could use perhaps a 2.2k to gnd and 3.3k to +5v to establish an
'indeterminate state' of 2v, then two voltage comparators on this signal
to check the voltage.  To make a window comparator, take two open-collector
comparator devices (such as LM396/LM339), connect minus-in on one comparator
to a voltage set to your lower threshold (e.g. 1.5v), plus-in on the other
comparator to your upper threshold (e.g. 2.25v), the two remaining inputs
together to the signal to be monitored, the two outputs together to a pullup
resistor, and off to your host.  The output goes high when the signal is
'in the window' (in your case 'tri-state').  Pullup again depends on your
application - perhaps 4.7k.   You set the voltage for the comparator 
thresholds using another resistor divider - perhaps +5v-18k-4.7k-10k-gnd.
Good Luck.

Regards
Steven Murray


-- 
Steven Murray
uunet!slxsys!stevem  stevem@specialix.co.uk
I must write out one thousand times "I will not leave myself logged in"
main{int a;for (a=0;a<1000;a++)printf("I must not leave myself logged in");}

whit@milton.u.washington.edu (John Whitmore) (06/05/91)

In article <1991Jun3.193519.19595@uokmax.ecn.uoknor.edu> sashahi@uokmax.ecn.uoknor.edu (Sandeep Shahi) writes:

>   Can anybody suggest a circuit which can separate a logic(0 or 1)
>from a tri state.
>		The output of such a circuit is to be read by the host
>for further action

	The obvious answer is to test the impedance of the pin; a 
220 pF capacitor and 2.2K ohm resistor in series from a square wave
generator can put a trickle of current into the pin (at some suitable
frequency), whereupon one can test with an XOR gate whether the
pin follows the square wave input (in which case it is tristate)
or not.  Remember that the XOR may have some race conditions,
so you must reject very narrow 'glitches' with a filter of some sort,
or by disabling the XOR's output sensor (an R/S flip-flop?) during
a brief period at each of the square wave's transitions.
	This will test the impedance of BOTH the pin and the tester;
you will want to use low-leakage gates to sense the pin (CMOS is
ideal).  Many tri-state circuits have termination resistors attached
so that the output stays HIGH unless more current is allowed (and
that will require a change of the resistor value cited above).

	In the old days, one simply had a termination resistor that
pulled the output into the TTL forbidden region (about 1.5V); no
logic LOW or logic HIGH gate would ever spend long at that voltage,
so a simple gate comparator would detect tri-state.  Alas, the
range of pullup resistor values nowadays is large, and the behavior
of some CMOS circuits with the inputs held in that range is terrible
(it can destroy the chip).  Unless you know the value of pullup
resistors on the tri-state lines, or unless you know there's no
CMOS that could be damaged, that technique is not reliable.

	John Whitmore

lamb@brahms.udel.edu (Richard E Lamb) (06/05/91)

true,
but for TTL tri-state, the terminator network approach works well...
as for determining when the pin is in the High Impedence state requires
use of the infamous MAYBE gate.  Don't know the 74XX number on these,
but you can make on easily from SSI stuff...

stevem@specialix.co.uk (Steven Murray) (06/10/91)

whit@milton.u.washington.edu (John Whitmore) writes:

>In article <1991Jun3.193519.19595@uokmax.ecn.uoknor.edu> sashahi@uokmax.ecn.uoknor.edu (Sandeep Shahi) writes:

>>   Can anybody suggest a circuit which can separate a logic(0 or 1)
>>from a tri state.
>>		The output of such a circuit is to be read by the host
>>for further action

>	The obvious answer is to test the impedance of the pin; a 
>220 pF capacitor and 2.2K ohm resistor in series from a square wave
>generator

[...stuff deleted]

>	In the old days, one simply had a termination resistor that
>pulled the output into the TTL forbidden region (about 1.5V); no
>logic LOW or logic HIGH gate would ever spend long at that voltage,
>so a simple gate comparator would detect tri-state.  Alas, the
>range of pullup resistor values nowadays is large, and the behavior
>of some CMOS circuits with the inputs held in that range is terrible
>(it can destroy the chip).  Unless you know the value of pullup
>resistors on the tri-state lines, or unless you know there's no
>CMOS that could be damaged, that technique is not reliable.

>	John Whitmore

Pullup resistors are also going to load the circuit you are suggesting
here.  The circuit you are suggesting can not give you a dynamic indication
of a circuits tri-state condition, as pulling to a mid-supply (e.g 2v val)
can.  CMOS circuits are very unlikely to be damaged by a mid-supply output!
If you are talking about a CMOS input the only time you get really excessive
current draw from a mid-supply CMOS input is when you have the chip on a
low Vcc (about 3v) - in any case values can be picked to ensure the 
'tristate voltage' is away from the transition point of the particular
logic families being used.

-Steven Murray


-- 
Steven Murray
uunet!slxsys!stevem  stevem@specialix.co.uk
I must write out one thousand times "I will not leave myself logged in"
main{int a;for (a=0;a<1000;a++)printf("I must not leave myself logged in");}