coln@hpl-opus.UUCP (02/24/87)
To program the 8251: The chip is programmed by writing a sequence of control words (bytes!) to the control register. 1) All programming goes to the same chip "address", so first you must insure that the chip is in a known state. One way to do this is a hardware reset, another is to write three "all zero" dummy bytes to the chip, and then a command instruction with the internal reset bit "one". (This covers the case where the first two may be interpreted as "sync" characters.) 2) Write a "mode" instruction to the control register: Assuming that you will use the chip in asynchronous mode: b7,b6 : stop bits : 00 invalid, 01 -> 1bit, 10 -> 1.5bits, 11 -> 2bits b5 : 0 -> odd parity, 1 -> even parity (only if parity enabled) b4 : 0 -> parity disabled, 1 -> parity enabled b3,b2 : character size : 00 -> 5bit, 01 -> 6bit, 10 -> 7bit, 11 -> 8bit b1,b0 : clock factor : 00 -> sync mode, 01 -> 1x, 10 -> 16x, 11 -> 64x 3) Write no "sync" characters, since I am assuming asynchronous operation. 4) Write a "command" instruction to the control register: b7 : 1 -> enter "hunt" mode (only for sync operation, no effect here) b6 : 1 -> internal reset, next write will be "mode" instruction b5 : 1 -> request-to-send output will go active (note active low) b4 : 1 -> reset error flags: parity, overrun, framing b3 : 1 -> send "break" character (force transmitted data to 0) b2 : 1 -> receive enable b1 : 1 -> data-terminal-ready output will go active (note active low) b0 : 1 -> transmit enable 5) now the chip should be working... Therefore, for your requested parameters of 7 data, parity, and 1 stop: 00000000 (sync) dummy sync if reading sync characters 00000000 (sync) second dummy sync 00000000 (command) dummy command 01000000 (command) internal reset 01111010 (mode) even parity or 01011010 odd parity, both 16x clock 00100111 (command) example with both RTS and DTR active I hope I got this right, and that it is the information you need. Mike Coln
herman@ti-csl.UUCP (02/24/87)
in article <1260@beta.UUCP>, dzzr@beta.UUCP (Douglas J Roberts) says: > > Does anybody know the commands for the 8251 USART? > I would like to tell the USART in my Z-80 CPM machine to > send serial data with 1 start bit, 7 data bits, 1 parity bit, and > one stop bit. > > The initialization routine in my bios sends 0CEH to the serial status > port which sets the UART to 2 stop bits, 16xclock, 8 data bits, no parity. > > If anybody knows the other control bytes, mucho appreciado! > > -- > Douglas J. Roberts, dzzr@lanl.gov > Los Alamos National Laboratory > Box 1663, F602 > Los Alamos, N. M. 87544 Mode format - async mode 0-1 Clock rate: 00 = sync mode, 01 = 1x, 10 = 16x, 11 = 64x 2-3 Char length: 00 = 5, 01 = 6, 10 = 7, 11 = 8 bits 4 Parity enable: 0 = disabled, 1 = enabled 5 Parity: 0 = odd, 1 = even 6-7 Stop bits: 00 = invalid, 01 = 1, 10 = 1.5, 11 = 2 Command instruction 0 Transmit enable: 1 = enable 1 Data Terminal Ready: 1 = ~DTR is forced low 2 Receive enable: 1 = enable 3 Send break character: 1 = TxD "low", 0 = normal operation 4 Error reset: 1 = Reset PE, OE and FE flags 5 Request to send: 1 = ~RTS is forced low 6 Internal reset: 1 = enter mode instruction format 7 Enter HUNT mode: 1 = enable search for sync chars Status byte 0 TxRDY: 1 = Transmitter ready for next character 1 RxRDY: 1 = Receiver ready - character waiting 2 TxEMPTY: 1 = Transmit buffer empty 3 PE: Parity Error 4 OE: Overrun Error 5 FE: Framing Error 6 SynDet: 1 = Sync character detected 7 DSR: 1 = Data Set Ready Bit #0 is the least significant bit; #7 is the most significant bit. The mode byte for 1 start bit, 7 data bits, odd parity, and 1 stop bit would be 05Ah (which includes the 16x clock factor too). -- Herman Schuurman ARPA: herman%TI-CSL@CSNET-RELAY.ARPA Texas Instruments Inc. CSNET: herman@TI-CSL PO Box 226015 M/S 238 USENET: {ut-sally,convex!smu,texsun,rice}!ti-csl!herman Dallas, Texas 75266 VOICE: (214) 995-0845