kenw%noah.arc.CDN@ean.ubc.ca (Ken Wallewein) (05/13/88)
I have a couple of Ithaca Intersystems 256KDR S-100 memory boards which I'd really like to use. 512 kb would be rather nice, and there's more where they came from. However, there's a wee problem. Or two. a) They use IEEE 696 24-bit addressing. Sounds great, right? Yeah, well, how do you do Z80-style bank switching? I can put 8-bit addresses on those lines, no problem. But HOW DO I KEEP A COMMON BANK? The Z80's going to want to keep some memory common, to execute in, won't it? The only thing I can think of is to hack up the board, moving the boards address bits 16 through 23 down one where they connect to the bus, putting them on 15 through 22, and tying the internal bit 15 low (I think). That would make everything show up in the low 32k only. Surely there's a better way...? b) The docs I have for them are a bit deficient: no schematics, and there are (is?) one dip switch and one jumper which are not even mentioned. The boards are identified as 1119-03. If anybody could belp be out, I sure would appreciate it! /kenw A L B E R T A Ken Wallewein R E S E A R C H kenw@noah.arc.cdn C O U N C I L ...I owe my soul to the company store...
del@Data-IO.COM (Erik Lindberg) (05/16/88)
In article <1481*kenw@noah.arc.cdn> kenw%noah.arc.CDN@ean.ubc.ca (Ken Wallewein) writes: > > I have a couple of Ithaca Intersystems 256KDR S-100 memory boards which I'd >really like to use. 512 kb would be rather nice, and there's more where they >came from. > Oh yeah? How can *I* get some? >keep some memory common, to execute in, won't it? The only thing I can think >of is to hack up the board, moving the boards address bits 16 through 23 down >one where they connect to the bus, putting them on 15 through 22, and tying >the internal bit 15 low (I think). That would make everything show up in the >low 32k only. > > Surely there's a better way...? > You could do what I did. A little awkward, but the results were quite nice. Using a wire wrap board that allows orientation of a socket with no restrictions, place a 40 pin three level W/W socket such that it's pins can be inserted into the CPU board Z80 socket, sandwich style. Also place the TI MMU chip (it's a 40 pin chip, 7461x series) on the board somewhere. Put the Z80 on another W/W socket real close to the main CPU socket, and connect all same-numbered pins together, except the ones that need to be interrupted to the MMU chip. A little bit of decode logic and you're in business: A two board CPU sandwich that allows you to map any 4k block in 24 bit space to any 4k block in 16 bit space. In the interest of simplicity, I recommend that you do not attempt to implement the register read features of the chip. It will conflict with the on board buffers of the main CPU and cause you no end of grief if you try. Also, since the data bus of the mapping chip during map register access is also the address bus input, I found that rather than buffering and steering the data bus it was far easier to just program the chip through the address bus of the Z80. It is a seldom used feature of the Z80, but you can write to a port while generating an 8 bit port address on the low byte of the address bus, while putting another register on the high byte of the address bus. That register will be either the "A" or the "B" register, depending on which output instruction you are using. I have actually implemented this kludge on the Computime Z80 CPU board. I got carried away and put a DMA chip and SCSI interface on the W/W board, since it bugged me to see all that wasted real-estate. Unfortunately, the added capacitive loading of the extra chips and wiring made the system unreliable at 6Mhz, and I had to throttle back to 4Mhz. Grumble. In retrospect, board real-estate is cheap ($35) I would have been better off just using two W/W boards. -- del (Erik Lindberg) uw-beaver!tikal!pilchuck!del
riddle@drivax.UUCP (Riddle) (05/18/88)
I liked <898@pilchuck.Data-IO.COM>'s solution to the S-100 24-bit addressing to the old Z80-bank switching kludge. Ithaca Intersystems took a simular approch, the CPU board had a simple MMU which provided 8 banks of 16 4K memory address translation. That's how MP/M and banked CP/M plus were implimented to look like a banked system, while DMA was still 24-bit addresses. BUT........I have an easier (better :-)) fix for you people with Cromemco or Advanced Micro type CPUs. I will provide you schmatics of a one chip addition to the 256K board, so that it will read the bank switch lines from the S-100 bus. .........BONUS........make board into 1 meg.............BONUS............ It will also show how add address decoding for using 256K mem chips, giving you 1 meg capacity on the board. I can't/won't character draw it here, so Email me your Postal address and I will USMail a copy to you. Riddle -- [replace with your own cute .signature] amdahl!drivax!riddle